17
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
NOTE: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means
device is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C, and 15ns cycle time.
5. This parameter is sampled.
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
T
A = 25°C; f = 1 MHz;
CI
34
pF
5
Input/Output Capacitance (DQ)
VDD = 3.3V
CO
45
pF
5
Address Capacitance
CA
3
3.5
pF
5
Clock Capacitance
CCK
3
3.5
pF
5
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C
≤ T
A ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-7.5
-8.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
≤ VIL
Current: Operating
or
≥ VIH; Cycle time ≥ tKC (MIN);
IDD
155
375
325
250
mA
2, 3, 4
VDD = MAX; Outputs open
Power Supply
Device selected; VDD = MAX;
Current: Idle
ADSC#, ADSP#, ADV#, GW#, BWx#
≥
IDD1
35
100
85
65
mA
2, 3, 4
VIH; All inputs
≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time
≥ tKC (MIN); Outputs open
CMOS Standby
Device deselected; VDD = MAX;
All inputs
≤ VSS + 0.2 or ≥ VDD - 0.2;
ISB2
0.4
10
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; VDD = MAX;
All inputs
≤ VIL or ≥ VIH;ISB3
8
252525
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#, BWx#
≥
ISB4
35
100
85
65
mA
3, 4
VIH; All inputs
≤ VSS + 0.2 or ≥
VDD - 0.2; Cycle time
≥ tKC (MIN)
MAX