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参数资料
| 型号： | NAND01GW3B2CN1E |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件页数： | 37/65页 |
| 文件大小： | 1473K |
| 代理商： | NAND01GW3B2CN1E |
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Software algorithms
NAND01G-B2C
8.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
8.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
●
First level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
●
Second level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
8.5
Error correction code
Users must implement an error correction code (ECC) to identify and correct errors in data
stored in NAND flash memories. The ECC implemented must be able to correct 1 bit every
512 bytes. Sensible data stored in spare area must be covered by ECC as well.
8.6
Hardware simulation models
8.6.1
Behavioral simulation models
Denali Software Corporation models are platform independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND flash devices, and so allow
software to be developed before hardware.
8.6.2
IBIS simulation models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
相关PDF资料 |
PDF描述 |
|---|---|
| NAND04GR3B3AN6 | 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND512W3B3BZA1F | 64M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND512W3B3CV1 | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND01GR4B3AV1F | 64M X 16 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND01GW4B3CZA1E | 64M X 16 FLASH 3V PROM, 35 ns, PBGA63 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GW3B2CN1F | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory |
| NAND01GW3B2CN6 | 制造商:STMicroelectronics 功能描述:128M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND01GW3B2CN6E | 功能描述:IC FLASH 1GBIT 48TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ |
| NAND01GW3B2CN6F | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory |
| NAND01GW3B2CWFD | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
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