参数资料
| 型号： | NCP1015ST65T3G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC OFFLINE SWIT SMPS CM SOT223 |
| 标准包装： | 4,000 |
| 输出隔离： | 隔离 |
| 频率范围： | 59kHz ~ 71kHz |
| 输入电压： | 8.1 V ~ 10 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 19W |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | TO-261-4，TO-261AA |
| 供应商设备封装： | SOT-223 |
| 包装： | 带卷 (TR) |
NCP1015
Rhold
0.1 m F
OVP
10 k
10 k
12 k
BAT54
+
CV CC
1
2
3
4
8
7
5
Transformer
Figure 23. Two Bipolar Transistors Ensures a Total Latch ? off of the SMPS in Presence of an OVP
R q JA
R hold ensures that the SCR stays on when fired. The bias
current flowing through R hold should be small enough to let
the V CC ramp up (8.5 V) and down (7.5 V) when the SCR
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolar can be MMBT2222 and
MMBT2907 for the discrete latch. The NST3946 features
T J(max) * T AMB(max)
P max + (eq. 12)
which gives around 1 W for an ambient of 50 ° C. The losses
inherent to the MOSFET R DS(on) can be evaluated using the
following formula:
two bipolar NPN + PNP in the same package and could also
be used.
3
P mos + 1 @ I p 2 @ D @ R DS(on)
(eq. 13)
Power Dissipation and Heatsinking
The power dissipation of NCP1015 consists of the
dissipation DSS current ? source (when active) and the
dissipation of MOSFET. Thus P tot = P DSS + P MOSFET .
When the PDIP7 package is surrounded by copper, it
becomes possible to drop its thermal resistance
junction ? to ? ambient, R q JA down to 75 ° C/W and thus
dissipate more power. The maximum power the device can
thus evacuate is:
where I p is the worse case peak current (at the lowest line
input), D is the converter operating duty ? cycle and R DS(on)
the MOSFET resistance for T J = 100 ° C. This formula is only
valid for Discontinuous Conduction Mode (DCM)
operation where the turn ? on losses are null (the primary
current is zero when you re ? start the MOSFET). Figure 24
gives a possible layout to help dropping the thermal
resistance. When measured on a 35 m m (1 oz.) copper
thickness PCB, we obtained a thermal resistance of 75 ° C/W:
Clamping Elements
DC
To Secondary Diode
Figure 24. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction ? to ? Ambient
Design Procedure
The design of a SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
1. In any case, the lateral MOSFET body ? diode shall
never be forward biased, either during start ? up
(because of a large leakage inductance) or in
normal operation as shown by Figure 25.
http://onsemi.com
14
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