参数资料
| 型号： | NCP1015ST65T3G |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/22页 |
| 文件大小： | 0K |
| 描述： | IC OFFLINE SWIT SMPS CM SOT223 |
| 标准包装： | 4,000 |
| 输出隔离： | 隔离 |
| 频率范围： | 59kHz ~ 71kHz |
| 输入电压： | 8.1 V ~ 10 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 19W |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | TO-261-4，TO-261AA |
| 供应商设备封装： | SOT-223 |
| 包装： | 带卷 (TR) |
NCP1015
8.5V
8.00
6.00
4.00
Vcc
7.5V
2.00
Device
internally
pulses
0
Startup period
Figure 13. The Charge/Discharge Cycle over a 10 m F V CC Capacitor
ICC1 @ t startup
D V
4V
As one can see, the V CC capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
reached before V CC crosses 7.5 V (otherwise the part enters
the fault condition mode). If we know that D V = 1 V and
ICC1 is 1.2 mA (for instance we selected a 11 W device
switching at 65 kHz), then the V CC capacitor can be
calculated using:
C w (eq. 1)
Let’s suppose that the SMPS needs 10 ms to startup, then
we will calculate C to offer a 15 ms period. As a result, C
the so ? called latch ? off level, where the current source
activates again to attempt a new re ? start. If the error has
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch ? off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short ? circuit. Figure 14
presents the corresponding diagram:
Current Sense
Information
should be greater than 18 m F thus the selection of a 33 m F /
16 V capacitor is appropriate.
Short Circuit Protection
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
FB
Division
Max
Ip
V CC
+
?
V CC(on)
To
Latch
Reset
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (V out is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g in a
short ? circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
Clamp
Active?
Flag
for the presence of the error flag every time V CC crosses
V CC(on) . If the error flag is low (peak limit not active) then
the IC works normally. If the error signal is active, then the
NCP1015 immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: V CC drops toward ground until it reaches
Figure 14. Simplified NCP1015 Short ? Circuit
Detection Circuitry
The protection burst duty ? cycle can easily be computed
through the various timing events as portrayed by Figure 15:
http://onsemi.com
8
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