参数资料
| 型号： | NCP1282BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK VM 16SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 占空比： | 85% |
| 电源电压： | 8.5 V ~ 20 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1282BDR2GOSCT |
NCP1282
V CSKIP(valley) once the CSKIP voltage reaches the turn on
threshold of the latch. The external latch is cleared by
bringing the UVOV voltage below V UV and disabling V REF .
V REF
is usually filtered using an RC low–pass filter to avoid
premature triggering of the current limit circuit. However,
the low pass filter will inevitably change the shape of the
current pulse and also add cost and complexity. The
NCP1282 uses LEB circuitry that blocks out the first 70 ns
C REF
OUTY
V CC
INA
(typ) of each current pulse. This removes the leading edge
spikes without altering the current waveform. The blanking
period is disabled during soft-- start as the blanking period
may be longer than the startup duty cycle. It is also disabled
CSKIP
C CSKIP
OE
MC74VHC1GT126
if the output of the Saturation Comparator is low, indicating
that the output is not yet in regulation. This occurs during
power up or during an output overload condition.
Figure 38. External Latch Implemented using
ON Semiconductor’s MiniGate t Buffer
The latch in Figure 38 consists of a TTL level tri-- state
output buffer from ON Semiconductor ’s MiniGate t
family. The enable (OE) and output (OUTY) terminals are
connected to CSKIP and the V CC and INA pins are
connected to V REF . The output of the buffer is in a high
impedance mode when OE is low. Once a continuous
current limit condition is detected, the CSKIP timer is
enabled and CSKIP begins charging. Once the voltage on
CSKIP reaches the enable threshold of the buffer, the
output of the buffer is pulled to V REF , latching the CSKIP
timer. The OE threshold of the buffer is typically 1.5 V.
V REF
Supply Voltage and Startup Circuit
The NCP1282 internal startup regulator eliminates the
need for external startup components. In addition, this
regulator increases the efficiency of the supply as it uses no
power when in the normal mode of operation, but instead
uses power supplied by an auxiliary winding. The
NCP1282 incorporates an optimized startup circuit that
reduces the requirement of the supply capacitor,
particularly important in size constrained applications.
The minimum supply voltage of the NCP1282 is
optimized for driving high voltage MOSFETs. It is not
uncommon for high voltage MOSFETs to have a gate
plateau voltage of 6 V. In addition, high voltage
applications may require a high side drive circuit with a
voltage drop of up to two diodes. If the minimum supply
voltage is too low, there may not be enough voltage for
C REF BSS84L
M2
24.9 k Ω
R pull--up
driving the external MOSFETs causing the system to
malfunction. The NCP1282 eliminates this problem with a
minimum supply voltage of 8.5 V.
The startup regulator consists of a constant current
CSKIP
C CSKIP
M1
2N7002L
source that supplies current from the input line voltage
(V in ) to the supply capacitor on the V AUX pin (C AUX ). The
startup current (I start ) is typically 10 mA.
Once C AUX is charged to 11.0 V (V AUX(on) ), the startup
regulator is disabled and the outputs are enabled if there are
no UV, OV, CSKIP or thermal shutdown faults. The startup
Figure 39. External Latch Implemented using
Discrete N and P--Channel MOSFETs
A latch implemented using discrete N and P-- channel
MOSFETs is shown in Figure 39. The latch is enabled once
the CSKIP voltage reaches the threshold of M1. Once M1
turns on, it pulls low the gate of M2. CSKIP is then pulled
to V REF by M2. It is important to size R pull--up correctly. If
R pull--up is too big, it will not keep M2 off while V REF
charges. This will cause the controller to latch during initial
power-- up. In this particular implementation the turn on
threshold of M1 is 2 V and R pull--up is sized to 24.9 k ? .
Leading Edge Blanking
The current sense signal is prone to leading edge spikes
caused by the power switch transitions. The current signal
regulator remains disabled until the lower voltage
threshold (V AUX(off1) ) of 9.5 V is reached. Once reached,
the startup circuit is enabled and a soft-- stop event is
initiated. If the bias current requirement out of C AUX is
greater than the startup current, V AUX will discharge until
reaching the lower voltage threshold (V AUX(off2) ) of 8.5 V.
Upon reaching V AUX(off2) , the outputs are disabled. Once
the outputs are disabled, the bias current of the IC is
reduced, allowing V AUX to charge back up. This mode of
operation allows a dramatic reduction in the size of C AUX
as not all the power required for startup needs to be stored
by C AUX . This mode of operation is known as Dynamic
Self Supply (DSS). Figure 40 shows the relationship
between V AUX(on) , V AUX(off1) , V AUX(off2) and UV. As
shown in Figure 40, the outputs are not enabled until the
UV fault is removed and V AUX reaches V AUX(on) .
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16
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