参数资料
| 型号： | NCP1282BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK VM 16SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 占空比： | 85% |
| 电源电压： | 8.5 V ~ 20 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1282BDR2GOSCT |
NCP1282
The minimum value of R FF is determined by the FF
Ramp discharge current (I FF(D) ). The current through R FF
(I RFF ) should be at least ten times smaller than I FF(D) for a
sharp FF Ramp transition. Equations 3 and 4 are used to
determine R FF and C FF .
1.0 A. If a higher drive capability is required, an external
driver stage can be easily added as shown in Figure 46.
V AUX
Vin
0.1 × IFF(D)
≤ RFF
(eq. 3)
CFF =
ln
?
Vin
Vin --3 V
D
? × f × RFF
(eq. 4)
OUT1
or
OUT2
Output
where, f is the operating frequency. It is recommended to
bias the FF circuit with enough current to provide good
R EA (Optional)
20 k Ω
V EA
2 k Ω
-
+
noise immunity.
PWM Comparator
In steady state operation, the PWM Comparator adjusts
the duty cycle by comparing the error signal to the FF
Ramp. The error signal is fed into the V EA pin. The V EA pin
can be driven directly with an optocoupler without the need
of an external pullup resistor as shown in Figure 45. In
some instances, it may be required to have a pullup resistor
smaller than the internal resistor (R4) to adjust the gain of
the isolation stage. This is easily accomplished by
connecting an external resistor (R EA ) in parallel with R4.
R EA is connected between the V REF and V EA pins. The
effective pullup resistance is the parallel combination of
R4 and R EA .
V REF
PWM
Comparator
Feedback
Signal
270 k Ω
Figure 46. Discrete Boost Drive Stage
OUT1 drives the main MOSFET, and OUT2 drives a low
side P-- Channel active clamp MOSFET. A high side
N-- Channel active clamp MOSFET or a synchronous
rectifier can also be driven by inverting OUT2. OUT2 is
purposely sized smaller than OUT1 because the active
clamp MOSFET only sees the magnetizing current.
Therefore, a smaller active clamp MOSFET with less input
capacitance can be used compared to the main switch.
Once V AUX reaches V AUX(on) (typically 11.0 V), the
internal startup circuit is disabled and the outputs are
enabled if no faults are present. Otherwise, the outputs
remain disabled until the fault is removed and V AUX
reaches V AUX(on) . The outputs are disabled after a soft-- stop
sequence if V AUX is below V AUX(on) or if V AUX reaches
8.5 V.
The outputs are biased directly from V AUX and their high
state voltage is approximately V AUX . Therefore, the
auxiliary supply voltage should not exceed the maximum
gate voltage of the main or active clamp MOSFET.
0.2 V
+
--
FF
FF Ramp
3V
0V
The high current drive capability of the outputs will
generate inductance-- induced spikes if inductance is not
reduced on the outputs. This can be done by reducing the
connection length between the drivers and their loads and
using wide connections.
Figure 45. Optocoupler Driving V EA Input
The drive of the V EA pin is simplified by internally
incorporating a series diode and resistor. The series diode
provides a 0.7 V offset between the V EA input and the
PWM Comparator inverting input. It allows reaching zero
duty cycle without the need of pulling the V EA pin all the
way to GND. The outputs are enabled if the V EA voltage is
approximately 0.5 V above the valley of the FF Ramp.
Overlap Delay
The overlap delay prevents simultaneous conduction of
the main and active clamp MOSFETs. The secondary
output, OUT2, precedes OUT1 during a low to high
transition and trails OUT1 during a high to low transition.
Figure 47 shows the relationship between OUT1 and
OUT2.
Outputs
t D (Leading)
t D (Trailing)
The NCP1282 has two in-- phase output drivers with an
adjustable overlap delay (t D ). The main output, OUT1, has
a source resistance of 4.0 Ω (typ) and a sink resistance of
2.5 Ω (typ). The secondary output, OUT2, has a source and
a sink resistance of 12 Ω (typ). OUT1 is rated at a
maximum of 2.0 A and OUT2 is rated at a maximum of
http://onsemi.com
19
OUT1
OUT2
Figure 47. Output Timing Diagram
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