参数资料
| 型号： | NCP1282BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK VM 16SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 占空比： | 85% |
| 电源电压： | 8.5 V ~ 20 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1282BDR2GOSCT |
NCP1282
The SYNC pin is in a high impedance mode during the
charging of the RTCT Ramp. In this period the oscillator
accepts an external SYNC pulse. If no pulse is detected
upon reaching the peak of the RTCT Ramp, a 100 ns SYNC
pulse is generated. The SYNC pulse is generated by
internally pulling the SYNC pin to V REF . The peak voltage
of the SYNC pin is typically 4.3 V. Once the 100 ns timer
expires, the pin goes back into a high impedance mode and
Two NCP1282’s are synchronized by connecting their
SYNC pins together. The first device that generates a sync
pulse during powerup becomes the master. A diode
connected as shown in Figure 50 can be used to
permanently set one controller as the master. The diode
prevents the master from receiving the SYNC pulse of the
slave controller.
an external resistor is required for pulldown as shown in
Figure 49.
V REF
MASTER
CONTROLLER
SYNC
R SYNC1
SYNC
R SYNC2
SLAVE
CONTROLLER
R T
RTCT
C T
SYNC
R SYNC
Figure 49. SYNC Pulse
The slew rate of the sync pin is determined by the pin
capacitance and external pulldown resistor. The maximum
source current of the SYNC pin is 1.0 mA. The resistor is
sized to allow the SYNC pin to discharge before the start
of the next cycle.
If an external pulse is received on the SYNC pin before
the internal pulse is generated, the controller enters the
slave mode of operation. Once operation in slave mode
commences, C T begins discharging and the R T C T Ramp
upper threshold is increased to 4.0 V.
If a controller in slave mode does not receive a sync pulse
before reaching the R T C T Ramp peak voltage (4.0 V), the
upper threshold is reset back to 3.0 V and the converter
reverts to operation in master mode. To guarantee the
converter stays in slave mode, the minimum clock period
Figure 50. Master--Slave Configuration
5.0 V Reference
The NCP1282 has a precision 5.0 V reference output. It
is a buffered version of the internal reference. The 5.0 V
reference is biased directly from V AUX and it can supply up
to 5.0 mA. Load regulation is 50 mV and line regulation is
100 mV within the specified operating range.
It is required to bypass the reference with a capacitor.
The capacitor is used for compensation of the internal
regulator and high frequency noise filtering. The capacitor
should be placed across the V REF and GND pins. In most
applications a 0.1 m F will suffice. A bigger capacitor may
be required to reduce the voltage ripple caused by the
oscillator current. The recommended capacitor range is
between 0.047 m F and 1.0 m F.
During powerup, the 5.0 V reference is enabled once
V AUX reaches V AUX(on) and a UV fault is not present.
Otherwise, the reference is enabled once the UV fault is
removed and V AUX reaches V AUX(on) .
Once a UV fault is detected after the reference has been
enabled, the reference is disabled after the soft-- stop
sequence is complete if the UV fault is still present. If the
UV fault is removed before soft-- stop is complete, the
reference is not disabled.
of the master controller has to be less than the R T C T charge
time from 2.0 V to 4.0 V.
http://onsemi.com
21
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