参数资料
型号: NCP1282BDR2G
厂商: ON Semiconductor
文件页数: 20/22页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK VM 16SOIC
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1MHz
占空比: 85%
电源电压: 8.5 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 剪切带 (CT)
其它名称: NCP1282BDR2GOSCT
NCP1282
The output overlap delay is adjusted by connecting a
resistor, R D , from the t D pin to ground . The overlap delay
is proportional to R D . A minimum delay of 20 ns is
obtained by grounding the t D pin.
The leading delay is purposely made longer than the
trailing delay. This allows the user to optimize the delay for
voltage (V RTCT(valley) ), typically 2.0 V, I RTCT turns OFF
allowing C T to charge back up through R T . The resulting
waveform on the RTCT pin has a sawtooth like shape.
V REF
the turn on transition of the main switch and ensure the
active clamp switch always exhibits zero volt switching.
R TCT
R T
3V
Analog and Power Ground (PGND)
The NCP1282 has an analog ground, GND, and a power
ground, PGND, terminal. GND is used for analog
Enable
I RTCT
C T
2V
? ?
VRTCT(valley)--VREF
tRTCT(C) = RTCT × ln
connections such as V REF , R T C T , feedforward among
others. PGND is used for high current connections such as
the internal output drivers. It is recommended to have
independent analog and power ground planes and connect
them at a single point, preferably at the ground terminal of
the system. This will prevent high current flowing on
PGND from injecting noise in GND. The PGND
connection should be as short and wide as possible to
reduce inductance-- induced spikes.
Oscillator
The oscillator frequency and maximum duty cycle are
set by an R T C T divider from V REF as shown in Figure 48.
A 500 m A current source (I RTCT ) discharges the timing
capacitor (C T ) upon reaching its peak threshold
(V RTCT(peak) ), typically 3.0 V. Once C T reaches its valley
Figure 48. Oscillator Configuration
OUT2 is set high once V RTCT(valley) is reached, followed
by OUT1 delayed by the overlap delay. Once V RTCT(peak)
is reached, OUT1 goes low, followed by OUT2 delayed by
t D .
The duty cycle is the C T charge time (t RTCT(C) ) minus the
overlap delay over the total charge and discharge (t RTCT(D) )
times. The charge and discharge times are calculated using
Equations 5 and 6. However, these equations are an
approximation as they do not take into account the
propagation delays of the internal comparator.
(eq. 5)
VRTCT(peak)--VREF
?
tRTCT(D) = RTCT × ln
(IRTCT × RT) + VRTCT(peak)--VREF
(IRTCT × RT) + VRTCT(valley)--VREF
?
(eq. 6)
tRTCT(C) + tRTCT(D)
The duty cycle, DC, is given by Equation 7.
tRTCT(C)--tD
D =
(eq. 7)
Substituting Equations 5, 6, and 7, and after a little
algebraic manipulation and replacing values, it simplifies
to:
? ? --
ln
?
× (I
D =
ln
?
VRTCT(valley)--VREF tD
VRTCT(peak)--VREF RTCT
VRTCT(valley)--VREF (IRTCT × RT) + VRTCT(peak)--VREF
VRTCT(peak)--VREF RTCT × RT) + VRTCT(valley)--VREF
(eq. 8)
It can be observed that D is set by R T , C T and t D . This
equation has two variables and can be solved iteratively. In
general, the time delay is a small portion of the ON time and
can be ignored as a first approximation. R T is then selected
to achieve a given duty cycle. Once the R T is selected, C T
is chosen to obtain the desired operating frequency using
Equation 9.
?
× (I
f =
RTCT × ln
?
VRTCT(valley)--VREF
VRTCT(peak)--VREF
1
(IRTCT × RT) + VRTCT(peak)--VREF
RTCT × RT) + VRTCT(valley)--VREF
(eq. 9)
Figures 23 through 26 show the frequency and duty cycle
variation vs R T for several C T values. R T should not be less
than 6.0 k Ω . Otherwise, the R T C T charge current will
exceed the pulldown current and the oscillator will be in an
undefined state.
Synchronization
A proprietary bidirectional frequency synchronization
architecture allows multiple NCP1282 to synchronize in a
master-- slave configuration. It can synchronize to
frequencies above or below the free running frequency.
http://onsemi.com
20
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