参数资料
| 型号： | NCP1282BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK VM 16SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 占空比： | 85% |
| 电源电压： | 8.5 V ~ 20 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1282BDR2GOSCT |
NCP1282
The line voltage is sampled using a resistor divider as
shown in Figure 42.
Vin(UV) = VUV ×
(R1 + R2)
R2
(eq. 1)
+
V OVCOMP
+
V UVCOMP
Vin(OV) = VOV
+ (Ioffset(UVOV) × R1)
R2
R1
R2
V in
UVOV
C UVOV
+
--
+
--
+
--
OV Comparator
-
3.0 V
UV Comparator
-
2.0 V
+
-
2.5 V
(R1 + R2)
(eq. 2)
The undervoltage threshold is trimmed during
manufacturing to obtain ? 3% accuracy allowing a tighter
power stage design.
Once the line voltage is within the operating range, and
V AUX reaches V AUX(on) , the outputs are enabled and a
soft-- start sequence commences. If a UV or OV fault is
detected afterwards, the converter enters a soft-- stop mode.
A small capacitor is required (>1000 pF) from the
UVOV pin to GND to prevent oscillation of the UVOV pin
and filter line transients.
Line Feedforward
I offset(UVOV)
Figure 42. Line UVOV Detectors
A UV condition exists if the UVOV voltage is below
V UV , typically 2.0 V. The ratio of R1 and R2 determines the
UV turn threshold. Once the UVOV voltage exceeds 2.5 V,
an internal current source (I offset(UVOV) ) sinks 50 m A into
the UVOV pin. This will clamp the UVOV voltage at 2.5 V
while the current across R1 is less than I offset(UVOV) . If the
input voltage continues to increase, the 50 m A source will
be overridden and the voltage at the UVOV pin will
increase. An OV condition exists if the UVOV voltage
exceeds V OV , typically 3.0 V. Figure 43 shows the
relationship between UVOV and V in .
The NCP1282 incorporates line feedforward (FF) to
limit the maximum volt-- second product. It is the line
voltage times the ON time. This limit prevent saturation of
the transformer in forward and flyback topologies. Another
advantage of feedforward is a controller frequency gain
independent of line voltage. A constant gain facilitates
frequency compensation of the converter.
Feedforward is implemented by generating a ramp
proportional to V in and comparing it to the error signal. The
error signal solely controls the duty cycle while the input
voltage is fixed. If the line voltage changes, the FF Ramp
slope changes and duty cycle is immediately adjusted instead
of waiting for the change to propagate around the feedback
loop and be reflected back on the error signal.
The FF Ramp is generated with an R-- C (R FF C FF ) divider
from the input line as shown in Figure 44. The divider is
selected such that the FF Ramp reaches 3.0 V in the desired
maximum ON time. The FF Ramp terminates by
effectively grounding C FF during the converter OFF time.
This can be triggered by the FF Ramp reaching 3.0 V, or
any other condition that limits the duty cycle.
V in
V UVCOMP
To PWM and VS
Comparators
R FF
I RFF
3V
FF
V UVOV
V OVCOMP
FF Reset
I FF(D)
C FF
t on
T
0V
Time
Figure 43. UVOV Detectors Typical Waveforms
While the internal current source is disabled, the UVOV
voltage is solely determined by the ratio of R1 and R2. The
input voltage at which the converter turns ON is given by
Equation 1. Once the internal current source is enabled, the
Figure 44. Feed Forward Ramp Generation
The FF pin is effectively grounded during power or
during standby mode to prevent the FF pin from charging
up to V in .
absolute value of R1 together with the ratio of R1 and R2
determine the turn OFF threshold as shown in Equation 2.
http://onsemi.com
18
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