参数资料
| 型号： | NCP5218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/31页 |
| 文件大小： | 0K |
| 描述： | IC DDR PWR CTLR 2IN2 NTBK 22-DFN |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR |
| 输入电压： | 4.5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 22-VFDFN 裸露焊盘 |
| 供应商设备封装： | 22-DFN（6x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
NCP5218
DETAILED OPERATING DESCRIPTION
General
The NCP5218 2 ? in ? 1 Notebook DDR Power Controller
combines the efficiency of a PWM controller for the V DDQ
supply, with the simplicity of using a linear regulator for the
V TT termination voltage power supply. The V DDQ output
can be adjusted through the external potential divider,
while the V TT is internally set to track half V DDQ .
The inclusion of V DDQ power good voltage monitor,
soft ? start, V DDQ overcurrent protection, V DDQ
overvoltage and undervoltage protections, supply
undervoltage monitor, and thermal shutdown makes this
device a total power solution for high current DDR memory
system. The IC is packaged in DFN22.
Control Logic
The internal control logic is powered by VCCA. The IC
is enabled whenever V DDQEN is high (exceed 1.4 V). An
internal bandgap voltage, V REF , is then generated. Once
V REF reaches its regulation voltage, an internal signal
V REFGD will be asserted. This transition wakes up the
supply undervoltage monitor blocks, which will assert
VCCAGD if VCCA voltage is within certain preset levels.
The control logic accepts external signals at VCCA,
OCDDQ, VDDQEN, VTTEN, and FPWM pins to control
the operating state of the V DDQ and V TT regulators in
accordance with Table 1. A timing diagram is shown in
Figure 38.
V DDQ Switching Regulator in Normal Mode (S0)
The V DDQ regulator is a switching synchronous
rectification buck controller directly driving two external
N ? Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM with external
compensation and with switching frequency fixed at
400 kHz " 15%. As can be observed from Figure 1, the
Table 1 . State, Operation, Input and Output Condition Table
V DDQ output voltage is divided down and fed back to the
inverting input of an internal error amplifier through
FBDDQ pin to close the loop at V DDQ = V FBDDQ ×
(1 + R1/R2). This amplifier compares the feedback voltage
with an internal V REF (= 0.800 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform
derived from the internal oscillator to generate a
pulse ? width ? modulated signal. This PWM signal drives
the external N ? Channel Power FETs via the TGDDQ and
BGDDQ pins. External inductor L and capacitor C OUT1
filter the output waveform. The V DDQ output voltage
ramps up at a pre ? defined soft ? start rate when the IC enters
state S0 from S5. When in normal mode, and regulation of
V DDQ is detected, signal IN REGDDQ will go HIGH to notify
the control logic block.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive nonoverlap timing control of the complementary
gate drive output signals is provided to reduce large
shoot ? through current that degrades efficiency.
Tolerance of V DDQ
The tolerance of V FBDDQ and the ratio of external
resistor divider R1/R2 both impact the precision of V DDQ .
With the control loop in regulation, V DDQ = V FBDDQ × (1
+ R1/R2). With a worst case (for all valid operating
conditions) V FBDDQ tolerance of " 1.5%, a worst case
range of " 2.5% for V DDQ = 1.8 V will be assured if the
ratio R1/R2 is specified as 1.2500 " 1%.
Input Conditions
Operating Conditions
Output Conditions
Mode
S5
S5
S0
S3
VCCA
Low
X
High
High
VOCDDQ
X
Low
High
High
VDDQEN
X
X
High
High
VTTEN
X
X
High
Low
FPWM
X
X
X
High
VDDQ
H ? Z
H ? Z
Normal
Standby
VTTREF
H ? Z
H ? Z
Normal
Normal
VTT
H ? Z
H ? Z
Normal
H ? Z
TGDDQ
Low
Low
Normal
Standby
BGDDQ
Low
Low
Normal
Standby
PGOOD
Low
Low
H ? Z
H ? Z
(Power ?
saving)
(Power ?
saving)
S3
S5
High
X
High
X
High
Low
Low
X
Low
X
Normal
H ? Z
Normal
H ? Z
H ? Z
H ? Z
Normal
Low
Normal
Low
H ? Z
Low
V DDQ Regulator in Standby Mode (S3)
During state S3, a power ? saving mode is activated when
the FPWM pin is pulled to VCCA. In power ? saving mode,
the switching frequency is reduced with the V DDQ output
current and the low ? side FET is turned off after the
detection of negative inductor current, so as to enhance the
http://onsemi.com
15
相关PDF资料 |
PDF描述 |
|---|---|
| NCP5220MNR2G | IC CTLR PWM DUAL BUCK PWR 20-DFN |
| NCP5222MNR2G | IC CTLR BUCK 2CH 2PH 28QFN |
| NCP5252MNTXG | IC REG BUCK SYNC ADJ 2A 16QFN |
| NCP5314FTR2G | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| NCP5318FTR2G | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NCP5220 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3−in−1 PWM Dual Buck and Linear Power Controller |
| NCP5220AMNR2 | 功能描述:DC/DC 开关控制器 3-in-1 PWM Dual Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5220AMNR2G | 功能描述:DC/DC 开关控制器 ANA DDR PWER CNTRLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5220MNR2 | 功能描述:DC/DC 开关控制器 3-in-1 PWM Dual Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5220MNR2G | 功能描述:DC/DC 开关控制器 3-in-1 PWM Dual Buck Linear DDR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
发布紧急采购，3分钟左右您将得到回复。