参数资料
型号: NCP5218MNR2G
厂商: ON Semiconductor
文件页数: 22/31页
文件大小: 0K
描述: IC DDR PWR CTLR 2IN2 NTBK 22-DFN
产品变化通告: Product Obsolescence 30/Sept/2009
标准包装: 2,500
应用: 控制器,DDR
输入电压: 4.5 V ~ 24 V
输出数: 2
输出电压: 可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 22-VFDFN 裸露焊盘
供应商设备封装: 22-DFN(6x5)
包装: 带卷 (TR)
NCP5218
gain is obtained by adding the modulator and filter gain (in
dB) to the compensation gain (in dB) . The bandwidth is the
frequency at which the gain is 0 dB and the phase margin
is the difference between the close loop phase and 180 ° .
The goal of compensation is to achieve a stable close loop
having ? 20 dB/decade slope at 0 dB gain crossing, and
sufficient phase margin for stability. The bandwidth of
close loop gain should be less than 50% of the switching
frequency and the compensation gain should be bounded
by the error amplifier open loop gain.
system with the highest possible bandwidth, the gain
VIN
NCP5218
VBOOST
TGDDQ
Q1
L
CIN
VDDQ
VDDQ
PWM
LOGIC
VCCP
PGND
SWDDQ
BGDDQ
Q2
ESR
COUT
OUTPUT
FILTER
PGND
OSC
PWM
COMP
COMP
VIN
ADAPTIVE VRAMP
RAMP
ERROR
AMP
A
VREF
C2
R3
C1
C3
R4
R1
COMPENSATION
NETWORK
FBDDQ
MODULATOR
R2
Figure 39. Voltage Mode Buck Converter with Modulator, LC filter and Type III Compensation
Modulator DC Gain can be calculated by:
Type III compensation poles and zeros break frequencies
VIN
GMOD(DC) + 20 log
fZ1 +
(eq. 20)
VRAMP
LC filter double pole and ESR zero break frequencies are
are defined by the below equations:
1
2 p R3
C2
(eq. 24)
fPLC +
1
fZESR +
1
2 p
ESR
COUT
fP1 +
2 p
R3
fZ2 +
fP2 +
GCOMP(DC) + 20 log 3
defined by:
(eq. 21)
2 p L COUT
(eq. 22)
Compensation network DC Gain can be calculated by the
equation:
R
(eq. 23)
R1
100
f Z1
2 p (R1 ) R4) C3
2 p R4 C3
1
1
1
C1  C2
C1 ) C2
(eq. 25)
(eq. 26)
(eq. 27)
80
60
40
20
f Z2
f P1
f P2
Open Loop Error
Amp Gain
Compensation
Gain
0
? 20
? 40
20 log
20 log
R3
R1
VIN
VRAMP
f ZESR
f PLC
Closed Loop Gain
Modulator & Filter Gain
? 60
10
100
1k
10 k 100 k 1 M
10 M
FREQUENCY (Hz)
Figure 40. Asymptotic Bode Plot of the Converter Gain
http://onsemi.com
22
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