参数资料
| 型号： | NCP5218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 25/31页 |
| 文件大小： | 0K |
| 描述： | IC DDR PWR CTLR 2IN2 NTBK 22-DFN |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR |
| 输入电压： | 4.5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 22-VFDFN 裸露焊盘 |
| 供应商设备封装： | 22-DFN（6x5） |
| 包装： | 带卷 (TR) |
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NCP5218
ESR v 100 mV + 14.3 m W (eq. 49)
Thus, inductor with 1.8 m H inductance, 14 A maximum
rated DC current and 3.5 m W DCR is chosen.
c. Calculate ESR and capacitance of output filter
capacitor:
First, the ESR required to achieve the desired output
ripple voltage is considered. Suppose the output ripple
voltage is 2% of the nominal output voltage.
Second, the ESR required to meet the transient load
undershoot requirement is considered, such that:
7A
Therefore, the suitable ESR is 12 m W or smaller, and the
value of 7.5 m W is selected for more design margin and
better performance. Then, two same SP ? Caps or POSCAPs
ESR v
(0.02 1.8 V) 1.8 m H
+ 15.8 m W
(20 V ? 1.8 V)
400 kHz
1.8 V
20 V
(eq. 48)
each with 15 m W ESR in parallel having a resultant ESR
of 7.5 m W should be good enough to meet the
requirements.
Then, check that whether the previously supposed
capacitance meets the undershoot and overshoot
requirements.
To ensure that undershoot requirement of less than 100 mV is achieved, the capacitance must be:
1 ? 1.8 V 20 V mV
COUT w
7A
100 mV ? 7 A
7.5 m W
? 36
400 kHz
+ 335.9 m F
(eq. 50)
To make sure that overshoot requirement of less than 100 mV is fulfilled, capacitance must be:
1.8 m H
7 A ) 2
COUT w
(20 V ? 1.836 V) 1.836 V
1.8 m H 400 kHz 20 V
(100 mV ) 1.836 V)2 ? (1.836 V)2
2
+ 317.6 m F
(eq. 51)
Vrated w 1.25
1.836 V + 2.3 V
ICOUT(rms) w
+ 2.3 A
1.8 m H 400 kHz 20 V
ILIMIT u 8 A ) 2 A )
RL1 + 11.5 A 10 m W + 4.4 k W (eq. 55)
Therefore, output capacitor with capacitance of 440 m F
should meet both undershoot and overshoot requirements.
Sometimes, it may take several times of iterations between
the process of selecting inductance of the inductor and ESR
and capacitance of the output capacitor.
Then, the voltage rating of the output capacitor is
estimated by:
(eq. 52)
Thus, output capacitor with 2.5 V or larger rated voltage
is used.
Finally, the rated rms ripple current of the output
capacitor is considered:
(20 V ? 1.836 V) 1.836 V
(eq. 53)
Thus, capacitor with rated rms ripple current of 3.0 A or
larger should be selected. Two capacitors each with 1.5 A
rated ripple current can be connected in parallel to provide
a total of 3.0 A rated rms ripple current.
Therefore, two same capacitors in parallel each with
capacitance of 220 m F, ESR of 15 m W , rated voltage of
2.5 V, and rated rms ripple current of 1.5 A are used.
d. Calculate the resistance value of OCP current limit
setting resistor:
First, the OCP current limit is estimated at maximum
load condition, such that:
(20 V ? 1.836 V) 1.836 V
2 1.8 m H 400 kHz 20 V
+ 11.16 A
(eq. 54)
Thus, I LIMIT is set to 11.5 A. Suppose from the high ? side
MOSFET data sheet, the maximum R DS(on) is 10 m W .
Then, the value of RL1 is calculated by:
26 m A
Therefore, the resistor with standard value of 4.7 k W is
selected for RL1.
e. Calculate the RC values of the compensation network:
First, 4.3 k W is chosen as the value of R 1 which is in the
range between 2.0 k W and 5.0 k W.
Since the worst case of stability is at the maximum V IN ,
the close loop compensation should be considered at
maximum V IN . Then the ramp amplitude can be calculated
as below:
VRAMP + 1.25 V ) 0.045 (20 V ? 5 V) + 1.925 V
(eq. 56)
Since the L = 1.8 m H, C OUT = 440 m F, and the target close loop bandwidth is 100 kHz, the value of R 3 can be
calculated as:
R3 +
2 p
100 kHz
1.925 V
4.3 k W
20 V
1.8 m H
440 m F
+ 7.3 k W
(eq. 57)
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