参数资料
| 型号： | NCP5218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 27/31页 |
| 文件大小： | 0K |
| 描述： | IC DDR PWR CTLR 2IN2 NTBK 22-DFN |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR |
| 输入电压： | 4.5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 22-VFDFN 裸露焊盘 |
| 供应商设备封装： | 22-DFN（6x5） |
| 包装： | 带卷 (TR) |
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NCP5218
PCB Layout Guidelines
Cautious PCB layout design is very critical to ensure
high performance and stable operation of the DDR power
controller. The following items must be considered when
preparing PCB layout:
1. All high ? current traces must be kept as short and
wide as possible to reduce power loss.
High ? current traces are the trace from the input
voltage terminal to the drain of the high ? side
MOSFET, the trace from the source of the
high ? side MOSFET to the inductor, the trace
from inductor to the V DDQ output terminal, the
trace from the input ground terminal to the V DDQ
output ground terminal, the trace from V DDQ
output to VTTI pin, the trace from VTT pin to
V TT output terminal, and the trace from V TT
output ground terminal to the VTTGND pin.
Power handling and heaksinking of high ? current
traces can be improved by also routing the same
high ? current traces in the other layers and joined
together with multiple vias.
2. Power components which include the input
capacitor, high ? side MOSFET, low ? side
MOSFET and V DDQ output capacitor of the buck
converter section must be positioned close
together to minimize the current loop. The input
capacitor must be placed close to the drain of the
high ? side MOSFET and the source of the
low ? side MOSFET.
3. To ensure the proper function of the device,
separated ground connections should be used for
different parts of the application circuit according
to their functions. The input capacitor ground, the
low ? side MOSFET source, the V DDQ output
capacitor ground, the VCCP decoupling capacitor
ground should be connected to the PGND. The
trace path connecting the source of the low ? side
MOSFET and PGND pin should be minimized.
The V TT output capacitor ground should be
connected to the VTTGND first with a short
trace, it is then connected to the ground plane of
PGND. The VCCA decoupling capacitor ground,
the ground of the V DDQ feedback resistor, the
soft ? start capacitor ground, the VTTREF output
capacitor ground should be connected to the
AGND. The AGND pin is then connected directly
through a sense trace to the remote ground sense
point of the PGND, which is usually the ground
of the local bypass capacitor for the load. Never
connect the AGND, PGND and VTTGND
together just under the thermal pad.
4. The thermal pad of the DFN22 package should be
connected to the ground planes in the internal
layer and bottom layer from the copper pad at top
layer underneath the package through six to eight
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
vias with 0.6 mm hole ? diameter to help heat
dissipation and ensure good thermal capability. It
is recommended to use PCB with 1 oz or 2 oz
copper foil. The thermal pad can be connected to
either PGND ground plane or AGND ground
plane but not both.
The input capacitor ground terminal, the V DDQ
output capacitor ground terminal and the source
of the low ? side MOSFET must be connected to
the PGND ground plane through multiple vias.
Sensitive traces like trace from FBDDQ, trace
from COMP, trace from OCDDQ, trace from
FBVTT and trace from VTTREF should be
avoided from the high ? voltage switching nodes
like SWDDQ, BOOST, TGDDQ and BGDDQ.
Separate sense trace should be used to connect
the V DDQ point of regulation, which is usually
the local bypass capacitor for load, to the
feedback resistor divider to ensure accurate
voltage sensing. The feedback resistor divider
should be place close to the FBDDQ pin.
Separate sense trace should be used to connect the
V TT point of regulation, which is usually the local
bypass capacitor for load, to the FBVTT pin.
Separate sense trace should be used to connect
the V DDQ point of regulation to the DDQREF pin
to ensure that the reference voltage to V TT is
accurately half of the V DDQ voltage.
The traces length between the gate driver outputs
and gates of the MOSFETs must be minimized to
avoid parasitic impedance.
To ensure normal function of the device, an RC
filter should be placed close to the VCCA pin and
a decoupling capacitor should be placed close to
the VCCP pin.
The copper trace area of the switching node which
includes the source of the high ? side MOSFET,
drain of the low ? side MOSFET and high voltage
side of the inductor should be minimized by using
short wide trace to reduce EMI.
A snubber circuit consists of a 3.3 W resistor and
1.0 nF capacitor may need to be connected across
the switching node and PGND to reduce the
high ? frequency ringing occurring at the rising
edge of the switching waveform to obtain more
accurate inductor current limit sensing of the
V DDQ buck converter. However, adding this
snubber circuit will slightly reduce the conversion
efficiency.
VTTI should be connected to V DDQ output with
wide and short trace if V DDQ is used as the
sourcing supply for V TT . An input capacitor of at
least 10 m F should be added close to the VTTI
pin and bypassed to VTTGND if external voltage
supply is used as the V TT sourcing supply.
http://onsemi.com
27
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