参数资料
| 型号： | NCP5218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/31页 |
| 文件大小： | 0K |
| 描述： | IC DDR PWR CTLR 2IN2 NTBK 22-DFN |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR |
| 输入电压： | 4.5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 22-VFDFN 裸露焊盘 |
| 供应商设备封装： | 22-DFN（6x5） |
| 包装： | 带卷 (TR) |
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NCP5218
efficiency of the V DDQ regulator at light loads. The
switching frequency can be reduced smoothly until it
reaches the minimum frequency at about 15 kHz.
Therefore, perceptible audible noise can be avoided at light
load condition.
In power ? saving mode, the low ? side MOSFET is turned
off after the detection of negative inductor current and the
converter cannot sink current. The power ? saving mode can
be disabled by pulling the FPWM pin to ground. Then, the
converter operates in forced ? PWM mode with fixed
switching frequency and ability to sink current.
Fault Protection of V DDQ Regulator
During state S0 and S3, external resistor (RL1) between
OCDDQ and V IN sets the overcurrent trip threshold for the
high ? side switch. An internal 31 m A current sink (IOC) at
OCDDQ pin establishes a voltage drop across this resistor
and develops a voltage at the non ? inverting input of the
current limit comparator. The voltage at the non ? inverting
input is compared to the voltage at SWDDQ pin when the
high ? side gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than that at the
non ? inverting input for 4 consecutive internal clock
cycles, an overcurrent condition occurs, during which, all
outputs will be latched off to protect against a
short ? to ? ground condition on SWDDQ or VDDQ. The IC
will be reset once VCCA or VDDQEN is cycled.
Feedback Compensation of V DDQ Regulator
The compensation network is shown in Figures 2 and 39.
V TT Active Terminator in Normal Mode (S0)
The V TT active terminator is a two ? quadrant linear
regulator with two internal N ? channel power FETs. It is
capable of sinking and sourcing at least 1.5 A continuous
current and up to 2.4 A transient peak current. It is activated
in normal mode in state S0 when the VTTEN pin is HIGH
and VDDQ is in regulation. Its input power path is from
VDDQ with the internal FETs gate drive power derived
from VCCA. The V TT internal reference voltage is derived
from the DDQREF pin. The VTT output is set to VDDQ/2
when V TT output is connecting to the FBVTT pin directly.
This regulator is stable with only a minimum 20 m F output
capacitor. The V TT regulator will have an internal
soft ? start when it is transited from disable to enable.
During the V TT soft ? start, a current limit is used as a current
source to charge up the V TT output capacitor. The current
limit is initially 1.0 A during V TT soft ? start. It is then
increased to 2.5 A after 128 internal clock cycles which is
V TT Active Terminator in Standby Mode (S3)
V TT output is high ? impedance in S3 mode.
Fault Protection of V TT Active Terminator
To provide protection for the internal FETs, bidirectional
current limit is implemented, preset at the minimum of
2.5 A magnitude.
Thermal Consideration of V TT Active Terminator
The V TT terminator is designed to handle large transient
output currents. If large currents are required for very long
duration, then care should be taken to ensure the maximum
junction temperature is not exceeded. The 5x6 DFN22 has
a thermal resistance of 35 ° C/W (dependent on air flow,
grade of copper, and number of vias). In order to take full
advantage from this thermal capability of this package, the
thermal pad underneath must be soldered directly onto a
PCB metal substrate to allow good thermal contact. It is
recommended that PCB with 2 oz. copper foil is used and
there should have 6 to 8 vias with 0.6 mm hole size
underneath the package’s thermal pad connecting the top
layer metal to the bottom layer metal and the internal layer
metal substrates of the PCB.
VTTREF Output
The V TTREF output tracks V DDQREF /2 at " 2% accuracy.
It has source current capability of up to 15 mA. V TTREF
should be bypassed to analog ground of the device by
1.0 m F ceramic capacitor for stable operation. The V TTREF
is turned on as long as V DDQREF is pulled high. In S0 mode,
V TTREF soft ? starts with V DDQ and tracks V DDQREF /2. In
S3 mode, V TTREF is kept on with V DDQ . V TTREF is turned
off only in S4/S5 like V DDQ output.
Output Voltages Sensing
The V DDQ output voltage is sensed across the FBDDQ
and AGND pins. FBDDQ should be connected through a
feedback resistor divider to the VDDQ point of regulation
which is usually the local V DDQ bypass capacitor for load.
The AGND should be connected directly through a sense
trace to the remote ground sense point which is usually the
ground of local V DDQ bypass capacitor for load.
The V TT output voltage is sensed between the FBVTT
and VTTGND pins. The FBVTT should be connected to
the V TT regulation point, which is usually the V TT local
bypass capacitor, via a direct sense trace. The VTTGND
should be connected via a direct sense trace to the ground
of the V TT local bypass capacitor for load.
typically 0.32 ms.
http://onsemi.com
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