参数资料
| 型号： | NCP5393BMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 2/3/4PHASE CPU 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，CPU |
| 输入电压： | 4.75 V ~ 5.25 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
NCP5393B
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0 ° C v T A v 70 ° C; 4.75 V v V CC v 5.25 V; All DAC Codes; C VCC = 0.1 m F)
Parameter
Test Conditions
Min
Typ
Max
Unit
PWRGOOD OUTPUT
PWRGOOD Upper Threshold
PWRGOOD Lower Threshold
V OUT Increasing, DAC = 1.3 V (Wrt DAC)
V OUT Decreasing, DAC = 1.3 V
?
?
300
350
?
?
mV
mV
PWM OUTPUTS (V DD & V DDNB )
Output Voltage (High)
Output Voltage (Low)
Rise and Fall Times
Tri ? State Output Leakage
Output Impedance ? HIGH or LOW
State
Sourcing 500 m A
Sinking 500 m A
C L = 50 pF, 0.7 V to 3.0 V or 3.0 V to 0.7 V
Gx = 2.5 V (x = 1 ? 4 or NB)
Resistance to V CC or GND
3.0
?
?
? 1.5
?
?
?
15
?
50
V CC
0.15
?
1.5
?
V
V
ns
m A
W
VDD REGULATOR 2/3/4 PHASE DETECTION
Gate Pin Source Current
Gate Pin Threshold Voltage
Phase Detect Timer
?
?
?
80
250
20
?
?
?
m A
mV
m s
SLEW RATE LIMITERS
Soft ? Start Slew Rate
Slew Rate Limit
In Any Mode During Soft ? Start
In Any Mode after Soft ? Start Completes
0.64
?
0.8
3.25
0.96
?
mV/ m s
mV/ m s
VID INPUTS (Note: In SVI Mode, VID[2] = Bidirectional “SVD’ Line and VID[3] = “SVC” Clock Input supporting AMD’s recommendation
in either fast ? mode I2C or high ? speed mode I2C)
VID Input Voltage (High)
VID Input Voltage (Low)
VID Hysteresis
Input Pulldown Current
SVD Output Voltage (Low)
V HIGH
V LOW
V HIGH ? V LOW or V LOW ? V HIGH
V IN = 0.6 V ? 1.9 V
In SVI Mode, I SINK = 5 mA
0.9
?
?
?
0
?
?
100
15
?
?
0.6
?
?
0.25
V
V
mV
m A
V
ENABLE INPUT
ENABLE Input Voltage (High)
ENABLE Input Voltage (Low)
Enable Hysteresis
Enable Input Pull ? Up Current
V HIGH
V LOW
Low ? High or High ? Low
Internal Pullup to V CC
2.0
?
?
?
?
?
200
15
?
0.8
?
?
V
V
mV
m A
VFIXEN INPUT (Active ? Low Input)
VFIXEN Input Voltage (High)
VFIXEN Input Voltage (Low)
VFIXEN Hysteresis
VFIXEN Input Pull ? Up Current
V HIGH
V LOW
Low ? High or High ? Low
Internal Pullup to V CC
0.9
?
?
?
?
100
15
?
0.6
?
V
V
mV
m A
PSI_L (Power Saving Phase Shed and Control, Active Low) (This pin is used in PVI mode only)
PSI_L Phase Shed Count (Note 4)
PSI_L Phase Shed Count (Note 4)
PSI_L Phase Shed Count (Note 4)
PSI_L Input Voltage (High)
PSI_L Input Voltage (Low)
PSI_L Hysteresis
Before Enable Assertion, No Phase Shedding while
PSI_L Active
Before ENABLE Assertion, Phase Shed to 2 Phases
Before ENABLE Assertion, Phase Shed to 1 Phase
After Soft ? Start, V HIGH
After Soft ? Start, V LOW
After Soft ? Start, V HIGH ? V LOW or V LOW ? V HIGH
?
0.9
1.3
0.9
?
?
?
?
?
?
100
0.6
1.1
?
?
0.6
V
V
V
V
V
mV
3. Guaranteed by design. Not production tested.
4. For guaranteed Phase Shed Count upon ENABLE assertion, set the PSI_L pin voltage range between the values shown for Min and
Max per the intended phase shed count.
http://onsemi.com
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