参数资料
| 型号： | NCP5393BMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 2/3/4PHASE CPU 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，CPU |
| 输入电压： | 4.75 V ~ 5.25 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
NCP5393B
ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0 ° C v T A v 70 ° C; 4.75 V v V CC v 5.25 V; All DAC Codes; C VCC = 0.1 m F)
Parameter
Test Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIERS (V DD & V DDNB )
Input Bias Current
? 200
?
200
nA
Input Offset Voltage (Note 3)
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current (Note 3)
Output Sink Current (Note 3)
V+ = V ? = 1.3V
C L = 60 pF to GND, R L = 10 k W to GND
C L = 60 pF to GND, R L = 10 k W to GND
C L = 60 pF to GND, R L = 10 k W to GND
D V IN = 100 mV, AV = ? 10 V/V,
1.5 V < V COMP < 2.5 V,
C L = 60 pF, DC Loading = $ 125 m A
10 mV of Overdrive, I SOURCE = 2.0 mA
10 mV of Overdrive, I SINK = 2.0 mA
10 mV of Overdrive, V OUT = 3.5 V
10 mV of Overdrive, V OUT = 1.0 V
? 1.0
?
?
?
?
3.5
?
?
?
?
80
15
70
5
?
?
2
2
1.0
?
?
?
?
?
1.0
?
?
mV
dB
MHz
deg
V/ m s
V
V
mA
mA
DIFFERENTIAL SUMMING AMPLIFIERS (V DD & V DDNB )
VS ? Input Bias Current
VS+ Input Resistance
VS+ Input Bias Voltage
VS ? Voltage at 0 V
DRVON = Low
DRVON = High
DRVON = Low
DRVON = High
33
1.0
7
0.37
0.05
m A
k W
V
VS+ Input Voltage Range (Note 3)
VS ? Input Voltage Range (Note 3)
? 3dB Bandwidth (Note 3)
C L = 80 pF to GND, R L = 10 k W to GND
? 0.3
? 0.3
?
?
15
3.0
0.3
V
V
MHz
DC gain, VS+ to DIFFOUT
DAC Accuracy (Measured at VS+)
VS+ to VS ? = 0.5 V to 2.35 V
Closed Loop Measurement, Error Amplifier Inside the
Loop.
1.0125 V v VDAC v 1.5500 V
0.8000 V v VDAC v 1.0000 V
12.5 mV v VDAC v 0.8000 V
0.982
? 0.5
? 5
? 8
1.0
?
?
?
1.022
0.5
5
8
V/V
%
mV
mV
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output source current (Note 3)
Output sink current (Note 3)
D V IN = 100 mV, D V OUT = 1.3 V ? 1.2 V
I SOURCE = 2 mA
I SINK = 2 mA
V OUT = 3 V
V OUT = 0.5 V
2.0
10
2.0
2.0
0.5
V/ m s
V
V
mA
mA
DROOP AMPLIFIERS (V DD & V DDNB )
Gain from Current Sense Input to
Droop Amplifier Output
Droop Amplifier DC Output Voltage
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current (Note 3)
Output Sink Current (Note 3)
0 mV < (CSx ? CSxN) < 60 mV
CSx = CSxN = 1.3 V
C L = 20 pF to GND, R L = 1 k W to GND
I SOURCE = 4.0 mA
I SINK = 1.0 mA
V OUT = 3.0 V
V OUT = 1.0 V
5.7
?
3.0
?
?
6.0
1.3
5.0
?
?
4.0
1.0
6.3
?
?
1.0
?
?
V/V
V
V/ m s
V
V
mA
mA
3. Guaranteed by design. Not production tested.
4. For guaranteed Phase Shed Count upon ENABLE assertion, set the PSI_L pin voltage range between the values shown for Min and
Max per the intended phase shed count.
http://onsemi.com
8
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