参数资料
型号: NCP5393BMNR2G
厂商: ON Semiconductor
文件页数: 6/24页
文件大小: 0K
描述: IC CTLR 2/3/4PHASE CPU 48QFN
标准包装: 2,500
应用: 控制器,CPU
输入电压: 4.75 V ~ 5.25 V
输出数: 1
输出电压: 0.013 V ~ 1.55 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5393B
NCP5393B PIN DESCRIPTIONS
Pin No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
FLAG
Symbol
NB_DROOP
NB_FB
NB_COMP
VID0
VID1
PWROK
ENABLE
VID3/SVC
VID2/SVD
PWRGOOD
NB_DRVON
DRVON
NB_G
G4
G3
G2
G1
PGND
Description
Voltage output signal proportional to total current drawn from the VDDNB regulator. Used when load
line operation (“droop”) is desired.
Voltage error amplifier inverting input for the V DDNB regulator.
Output of the voltage error amplifier for the V DDNB regulator.
Parallel Voltage ID DAC Input 0. Not used in SVI mode.
Parallel Voltage ID DAC Input 1. Also used for PVI or SVI mode selection.
System power supplies status input. Used in SVI mode only.
High = Run, Low = Standby/Reset.
Parallel Voltage ID DAC Input 1. Also used in SVI mode.
Parallel Voltage ID DAC Input 1. Also used in SVI mode.
Open drain output. High indicates that the active output(s) are within specification. Internally pulled
high by 5 m A to V CC
Bidirectional Gate Drive Enable to the gate driver for the V DDNB regulator.
Bidirectional Gate Drive Enable to gate drivers for the V DD regulator.
PWM output to the V DDNB gate driver.
PWM output #4. See Table: “Pin Connections vs. Phase Count”
PWM output #3. See Table: “Pin Connections vs. Phase Count”
PWM output #2. See Table: “Pin Connections vs. Phase Count”
PWM output #1. See Table: “Pin Connections vs. Phase Count”
High ? current power supply return via metal pad (flag) underneath package. The package flag should
be tied directly to Pin 2.
PIN CONNECTIONS VS. PHASE COUNT
Number of
CS4 &
CS3 &
CS2 &
CS1 &
Phases
4
3
2
G4
Phase 4
Out
Tie to
GND
Tie to
GND
G3
Phase 3
Out
Phase 3
Out
Phase 2
Out
G2
Phase 2
Out
Phase 2
Out
Tie to
GND
G1
Phase 1
Out
Phase 1
Out
Phase 1
Out
CS4N
Phase 4 CS
Input
Tie to GND
or V DD
Tie to GND
or V DD
CS3N
Phase 3 CS
Input
Phase 3 CS
Input
Phase 2 CS
input
CS2N
Phase 2 CS
Input
Phase 2 CS
Input
Tie to GND
or V DD
CS1N
Phase 1 CS
Input
Phase 1 CS
Input
Phase 1 CS
Input
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