参数资料
型号: NCP5393BMNR2G
厂商: ON Semiconductor
文件页数: 13/24页
文件大小: 0K
描述: IC CTLR 2/3/4PHASE CPU 48QFN
标准包装: 2,500
应用: 控制器,CPU
输入电压: 4.75 V ~ 5.25 V
输出数: 1
输出电压: 0.013 V ~ 1.55 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5393B
Functional Description
General
NCP5393B is a universal CPU hybrid power Controller
compatible with both Parallel VID interface (PVI) and
Serial VID interface (SVI) protocols for AMD Processors.
The Controller implements a single ? phase control
architecture to provide the Northbridge (NB) voltage on the
same chip. For the CORE section, programmable 2 ? to ? 4
phase featuring Dual ? Edge multiphase architecture is
implemented. It embeds two independent controllers for
CPU CORE and the integrated NB, each one with its set of
protections.
The NCP5393B incorporates differential voltage sensing,
differential phase current sensing, optional load ? line
voltage positioning, and programmable V DD and V DDNB
offsets to provide accurately regulated power parallel ? and
serial ? VID AMD processors. Dual ? edge multiphase
modulation provides the fastest initial response to dynamic
load events.
NCP5393B also supports V_FIX mode for board debug
and testing. In this particular configuration the SVI bus is
used as a static bus configuring four operative voltages
(through SVC and SVD) for both the sections and ignoring
any serial ? VID command.
NCP5393B is able to detect which kind of CPU is
connected and configures itself to work as a Single ? Plane
PVI controller or Dual ? Plane SVI controller.
Remote Output Sensing Amplifier (RSA)
A true differential amplifier allows the NCP5393B to
measure VCore voltage feedback with respect to the VCore
ground reference point by connecting the VCore reference
point to VSP, and the VCore ground reference point to VSN.
This configuration keeps ground potential differences between
the local controller ground and the VCore ground reference
point from affecting regulation of VCore between VCore and
VCore ground reference points. The RSA also subtracts the
DAC (minus VID offset) voltage, thereby producing an
unamplified output error voltage at the DIFFOUT pin. This
output also has a 1.3 V bias voltage as the floating ground to
allow both positive and negative error voltages.
Precision Programmable DAC
A precision programmable DAC is provided and system
trimmed. This DAC has 0.6% accuracy over the entire
operating temperature range of the part. The NCP5393B is
a Hybrid controller which supports both a six bit parallel
VID interface (PVI) and a seven bit serial VID interface
(SVI). The NCP5393B allows manufacturers to build a
motherboard that will accommodate either parallel or serial
VID processors in the same socket.
High Performance Voltage Error Amplifier
The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as the
controller of a voltage regulator, a capacitor from COMP to
Gate Driver Outputs and 2/3/4 Phase Operation
The part can be configured to run in 2 ? , 3 ? , or 4 ? phase
mode. In 2 ? phase mode, phases 1 and 3 should be used to
drive the external gate drivers, G2 and G4 must be grounded.
In 3 ? phase mode, gate output G4 must be grounded. In
4 ? phase mode all 4 gate outputs are used as shown in the
4 ? phase Applications Schematic. The Current Sense inputs
of unused channels should be connected to GND or to V DD .
Please refer to table “PIN CONNECTIONS vs. PHASE
COUNTS” for details.
Differential Current Sense Amplifiers and Summing
Amplifier
Four differential amplifiers are provided to sense the
output current of each phase. The inputs of each current
sense amplifier must be connected across the current sensing
element of the phase controlled by the corresponding gate
output (G1, G2, G3, or G4). If a phase is unused, the
differential inputs to that phase’s current sense amplifier
must be shorted together and connected to the GND or to
V DD .
The current signals sensed from inductor DCR are fed into
a summing amplifier to have a summed ? up output. The
outputs of current sense amplifiers control three functions.
First, the summing current signal of all phases will go
through DROOP amplifier and join the voltage feedback
loop for output voltage positioning. Second, the output
signal from DROOP amplifier also goes to ILIM amplifier
to monitor the output current limit. Finally, the individual
phase current contributes to the current balance of all phases
by offsetting their ramp signals of PWM comparators.
Oscillator and Triangle Wave Generator
The controller embeds a programmable precision
dual ? Oscillator: one section is used for the CORE and it is
a multiphase programmable oscillator managing equal
phase ? shift among all phases and the other section is used
for the NB section. The oscillator ’s frequency is
programmed by the resistance connected from the ROSC
pin to ground. The user will usually form this resistance
from two resistors in order to create a voltage divider that
uses the ROSC output voltage as the reference for creating
the current limit setpoint voltage. The oscillator frequency
range is 100 kHz per phase to 1.0 MHz per phase. The
oscillator generates up to 4 symmetrical triangle waveforms
with amplitude between 1.3 V and 2.3 V. The triangle waves
have a phase delay between them such that for 2 ? , 3 ? and
4 ? phase operation the PWM outputs are separated by 180,
120, and 90 angular degrees, respectively.
When the NB phase is enabled, in order to ensure that the
VDDNB oscillator does not accidentally lock to the VDD
oscillator, the VDDNB oscillator will free ? run at a
frequency which is nominally 1.25 ratio of f VDD .
VFB is required for stable unity gain test configurations.
http://onsemi.com
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