参数资料
型号: NCP5393BMNR2G
厂商: ON Semiconductor
文件页数: 5/24页
文件大小: 0K
描述: IC CTLR 2/3/4PHASE CPU 48QFN
标准包装: 2,500
应用: 控制器,CPU
输入电压: 4.75 V ~ 5.25 V
输出数: 1
输出电压: 0.013 V ~ 1.55 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5393B
NCP5393B PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
VCCA
GND
COMP
FB
DROOP
VS+
VS ?
OFFSET
DIFFOUT
VFIX
12VMON
PSI_L
CS1
CS1N
CS2
CS2N
CS3
CS3N
CS4
CS4N
ILIM
VCCB
NB_CS
NB_CSN
VID4
VID5
ROSC
NB_DIFFOUT
NB_OFFSET
NB_VS ?
NB_VS+
Description
5 V supply pin for the NCP5393B. The V CC bypassing capacitance must be connected between this
pin and GND (preferably returned to the package flag).
Small ? signal power supply return. This pin should be tied directly to the package flag (exposed pad).
Output of the voltage error amplifier for the V DD regulator.
Voltage error amplifier inverting input for the V DD regulator.
Voltage output signal proportional to total current drawn from the V DD regulator. Used when load line
operation (“droop”) is desired.
Non ? inverting input to the differential remote sense amplifier for the V DD regulator.
Inverting input to the differential remote sense amplifier for the V DD regulator.
Input for offset voltage to be added to the V DD DAC’s output voltage. Ground this pin for zero V DD
offset.
Output of the differential remote sense amplifier for the V DD regulator.
When pulled low, this pin causes the levels on the SVC (VID3) and SVD (VID2) pins to be decoded
as a two ? bit DAC code, which controls the V DD and VDDNB outputs. Internally pulled high by 5 m A to
V CC
UVLO monitor input for the 12 V power rail.
Determines number of phases operating in PSI_L mode. Phase shed count is locked upon ENABLE
assertion. After soft ? start, becomes power saving control in PVID mode. Low = phase shed
operation, High = normal operation.
Non ? inverting input to current sense amplifier #1 for the V DD regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #1 for the V DD regulator. See Table: “Pin Connections vs.
Phase Count”
Non ? inverting input to current sense amplifier #2 for the V DD regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #2 for the V DD regulator. See Table: “Pin Connections vs.
Phase Count”
Non ? inverting input to current sense amplifier #3 for the V DD regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #3 for the V DD regulator. See Table: “Pin Connections vs.
Phase Count”
Non ? inverting input to current sense amplifier #4 for the V DD regulator. See Table: “Pin Connections
vs. Phase Count”
Inverting input to current sense amplifier #4 for the V DD regulator. See Table: “Pin Connections vs.
Phase Count”
Overcurrent shutdown threshold for V DD and VDDNB. A resistor divider from ROSC to GND is
typically used to develop an appropriate voltage on ILIM.
5 V supply pin. Tie this pin to VCCA (Pin 1).
Non ? inverting input to the current sense amplifier for the VDDNB regulator
Inverting input to the current sense amplifier for the VDDNB regulator
Parallel Voltage ID DAC Input 4. Not used in SVI mode.
Parallel Voltage ID DAC Input 5. Not used in SVI mode.
A resistance from this pin to ground programs the V DD and VDDNB oscillator frequencies. This pin
supplies a trimmed output voltage of 2 V.
Output of the differential remote sense amplifier for the VDDNB regulator.
Input for offset voltage to be added to the VDDNB DAC’s output voltage. Ground this pin for zero
VDDNB offset.
Inverting input to the differential remote sense amplifier for the VDDNB regulator.
Non ? inverting input to the differential remote sense amplifier for the VDDNB regulator.
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