参数资料
型号: NCP5393BMNR2G
厂商: ON Semiconductor
文件页数: 17/24页
文件大小: 0K
描述: IC CTLR 2/3/4PHASE CPU 48QFN
标准包装: 2,500
应用: 控制器,CPU
输入电压: 4.75 V ~ 5.25 V
输出数: 1
输出电压: 0.013 V ~ 1.55 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5393B
DC IN
With ENABLE assertion, the PSI_L Phase Shed Strategy is Locked therefore
Voltages on PSI_L must be stable prior to ENABLE assertion.
VDDIO
ENABLE
PVIEN/
VID[1]
SVC/
VID[3]
SVD/
VR Turn ? On
Command
VID[1] Low at Rise of Enable Selects SVI Operation
BOOT VID MSB
VR Turn ? Off
Command
VID[2]
VDD and VDDNB
BOOT VID LSB
VR Turn ? Off
Command Forces
PWRGOOD Low
PWRGOOD
PWROK
Soft ? Start is
Complete
CPU Can Begin
Serial Data Xfer
Possible PWRGOOD
De ? Assertion
System Power Fault ?
Revert to BOOT VID
Outputs Rise to BOOT
VID at SS Rate
Resume Serial
VID Transactions
At end of soft ? start, PSI_L can be asserted
through the SVID protocal.
Figure 10. Power ? Up Sequence in Serial Mode Operation
PWRGOOD De ? Assertion
Causes System PWROK
De ? Assertion
Hardware Jumper Override ? V_FIX
VFIX is an active low pin and when it is pulled low, the
controller enters V_FIX mode. The voltage regulator can be
powered when an external SVI bus master is not present.
When in VFIX mode, all of the voltage regulator ’s output
voltages will be governed by the information shown in
Table 4, regardless of the state of PWROK. VFIX mode is
for debug only. If VFIX mode is necessary for processor
bring ? up, VFIXEN, SVC, and SVD should be connected
with jumpers to either ground or VDDIO through suitable
pull ? up resistors. SVC and SVD are considered as static
VID and the output voltage will change according to their
status.
Table 4. SVI VFIX VID CODES (TWO ? BIT PARALLEL)
SVC SVD V OUT (V)
0 0 1.4
0 1 1.2
? The system power sequence logic asserts the
NCP5393B ENABLE pin:
? The NCP5393B will sample the VID1 line to
determine whether to start in SVI or PVI mode.
? The NCP5393B samples the voltage on the PSI_L
pin in order to determine the desired operating
configuration during power saving mode.
? The Boot VID is dependent on SVI or PVI mode
startup.
? The NCP593A V DD regulator (and VDDNB if in SVID
mode) will soft ? start and ramp to the initial Boot VID.
? VFIXEN mode is entered once VFIXEN is asserted and
the V DD and VDDNB regulators will regulate to the
VFIXEN VID.
? VFIXEN VID is captured from decoding the voltages
on the VID3/SVC and VID2/SVD pins per Table 4.
? If VFIXEN is asserted prior to the VID controller
reaching the Boot VID, the VID controller will move to
1 0 1.0
1 1 0.8
The normal VFIXEN startup sequence for the NCP5393B
?
the VFIXEN VID.
If VFIXEN is de ? asserted, the evice PORs. This occurs
independent of ENABLE.
is as follows:
? 5 V is applied to the VCCA and VCCB pins to power
the NCP5393B and 12 V is applied to 12VMON.
? The NCP5393B samples the load on the G4 and G2
pins. If these pins are tied to ground the operating mode
will be altered from four phase mode, to three phase, or
PWROK De ? Assertion
Anytime PWROK de ? asserts while EN is asserted, the
controller uses the previously stored BOOT VID and
regulates all planes to that level performing an on ? the ? fly
transition to that level. PWRGOOD remains asserted in this
process.
two phase operation.
http://onsemi.com
17
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