参数资料
| 型号： | NCP5393BMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR 2/3/4PHASE CPU 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，CPU |
| 输入电压： | 4.75 V ~ 5.25 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
NCP5393B
Table 2. SIX ? BIT PARALLEL VID CODES in PVI Modes
SVID[5:0]
00_0000
00_0001
00_0010
00_0011
00_0100
00_0101
00_0110
00_0111
00_1000
00_1001
00_1010
00_1011
00_1100
00_1101
00_1110
00_1111
V OUT (V)
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
SVID[5:0]
01_0000
01_0001
01_0010
01_0011
01_0100
01_0101
01_0110
01_0111
01_1000
01_1001
01_1010
01_1011
01_1100
10_1101
01_1110
01_1111
V OUT (V)
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
SVID[5:0]
10_0000
10_0001
10_0010
10_0011
10_0100
10_0101
10_0110
10_0111
10_1000
10_1001
10_1010
10_1011
10_1100
10_1101
10_1110
10_1111
V OUT (V)
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6325
0.6250
0.6125
0.6000
0.5875
0.5750
SVID[5:0]
11_0000
11_0001
11_0010
11_0011
11_0100
11_0101
11_0110
11_0111
11_1000
11_1001
11_1010
11_1011
11_1100
11_1101
11_1110
11_1111
V OUT (V)
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
SVI ? Serial Interface
SVI is a two wire, Clock and Data, bus that connects a
single master (CPU) to one NCP5393B. The master initiates
and terminates SVI transactions and drives the clock, SVC,
and the data SVD, during a transaction. The slave receives
the SVI transactions and acts accordingly. SVI wire protocol
is based on fast ? mode I2C.
PWROK is proprietary of the SVI protocol and is
considered at start ? up. The SVI mode operation is explained
? The NCP5393B will sample the VID1 line to
determine whether to start in SVI or PVI mode.
SVID mode is determined when VID1 = Low.
? The NCP5393B samples the voltage on the PSI_L
pin in order to determine the desired operating
configuration during power saving mode.
? The Boot VID is captured from decoding the
voltages on the VID3/SVC and VID2/SVD pins per
in Figure 10. The VID codes from the decoded SVI value are
given in Table 3.
The normal SVI startup sequence for the NCP5393B is as
follows:
? 5 V is applied to the VCCA and VCCB pins to power
the NCP5393B and 12 V is applied to 12VMON.
? The NCP5393B samples the load on the G4 and G2
pins. If these pins are tied to ground the operating mode
will be altered from four phase mode, to three phase, or
two phase operation.
? The system power sequence logic asserts the
NCP5393B ENABLE pin:
?
?
?
?
?
Table 1 and stored.
The NCP5393B will start the VDD and VDDNB
regulators. Both regulators will soft start and ramp to
the Boot VID Voltage (See Table 1).
The NCP5393B asserts PWRGOOD.
The system asserts PWROK The system processor will
hold the boot VID voltage for at least 10us after
PWROK signal is asserted
Now the NCP5393B can accept new SVID codes on the
serial VID interface (See Table 3).
If the system should de ? assert PWROK, then the
NCP5393B will reset the Core and Northbridge VIDs
and regulate at the Boot VID voltage.
http://onsemi.com
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