参数资料
| 型号： | NCP5422ADR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP5422ADR2OS |
NCP5422A
The minimum inductance value for the input inductor is
therefore:
will be driven rail-to-rail due to overshoot caused by the
capacitive load they present to the controller IC.
LIN +
D V
(dI dt)MAX
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
where:
L IN = input inductor value;
D V = voltage seen by the input inductor during a full load
swing;
in the FET switch does not cause the power component to
exceed it's maximum rating.
The maximum RMS current through the switch can be
determined by the following formula:
(dI/dt) MAX = maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double-pole network
IRMS(H) +
IL(PEAK)2 ) (IL(PEAK)
) IL(VALLEY)2 D
3
IL(VALLEY))
fC +
with a slope of -2.0, a roll-off rate of -40 dB/dec, and a
corner frequency:
1
2 p LC
where:
L = input inductor;
C = input capacitor(s).
where:
I RMS(H) = maximum switching MOSFET RMS current;
I L(PEAK) = inductor peak current;
I L(VALLEY) = inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
SELECTION OF THE POWER FETS
PRMS(H) + IRMS(H)2
RDS(ON)
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1) Its very high input impedance ; and 2) Its very
fast switching times . The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven.
The input of the MOSFET acts as if it were a small capacitor,
where:
P RMS(H) = switching MOSFET conduction losses;
I RMS(H) = maximum switching MOSFET RMS current;
R DS(ON) = FET drain-to-source on-resistance
The upper MOSFET switching losses are caused during
MOSFET switch-on and switch-off and can be determined
by using the following formula:
PSWH + PSWH(ON) ) PSWH(OFF)
+ IN
which the driving circuit must charge at turn on. The lower
the drive impedance, the higher the rate of rise of V GS , and
V
IOUT
(tRISE ) tFALL)
6T
the faster the turn-on time. Power dissipation in the
switching MOSFET consists of 1) conduction losses, 2)
leakage losses, 3) turn-on switching losses, 4) turn-off
switching losses, and 5) gate-transitions losses. The latter
three losses are proportional to frequency.
The most important aspect of FET performance is the
Static Drain-To-Source On-Resistance (R DS(ON) ), which
affects regulator efficiency and FET thermal management
requirements. The On-Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On-Resistance also
increases. Its positive temperature coefficient is between
+0.6%/ ° C and +0.85%/ ° C. The higher the On-Resistance
the larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
where:
P SWH(ON) = upper MOSFET switch-on losses;
P SWH(OFF) = upper MOSFET switch-off losses;
V IN = input voltage;
I OUT = load current;
t RISE = MOSFET rise time (from FET manufacturer's
switching characteristics performance curve);
t FALL = MOSFET fall time (from FET manufacturer's
switching characteristics performance curve);
T = 1/f SW = period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)
where:
P HFET(TOTAL) = total switching (upper) MOSFET losses;
P RMS(H) = upper MOSFET switch conduction Losses;
P SWH(ON) = upper MOSFET switch-on losses;
P SWH(OFF) = upper MOSFET switch-off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
http://onsemi.com
12
TJ + TA ) [PHFET(TOTAL)
R q JA]
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