参数资料
| 型号： | NCP5422ADR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP5422ADR2OS |
NCP5422A
ELECTRICAL CHARACTERISTICS (0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; R OSC = 30.9 k, C COMP1,2 = 0.1 m F,
10.8 V < V CC < 13.2 V; 10.8 V < BST < 20 V, C GATE(H)1,2 = C GATE(L)1,2 = 1.0 nF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
V FB1(2) Bias Current
V FB1(2) Input Range
COMP1,2 Source Current
COMP1,2 Sink Current
Reference Voltage 1(2)
COMP1,2 Max Voltage
COMP1,2 Min Voltage
Open Loop Gain
Unity Gain Band Width
PSRR @ 1.0 kHz
Transconductance
Output Impedance
V FB1(2) = 0 V
-
COMP1,2 = 1.2 V to 2.5 V; V FB1(2) = 0.8 V
COMP1,2 = 1.2 V; V FB1(2) = 1.2 V
COMP1 = V FB1 ; COMP2 = V FB2
V FB1(2) = 0.8 V
V FB1(2) = 1.2 V
-
-
-
-
-
-
0
15
15
0.980
3.0
-
-
-
-
-
-
0.5
-
30
30
1.000
3.3
0.25
95
40
70
32
2.5
1.6
1.1
60
60
1.020
-
0.35
-
-
-
-
-
m A
V
m A
m A
V
V
V
dB
kHz
dB
mmho
M W
GATE(H) and GATE(L)
High Voltage (AC)
Measure: V CC - GATE(L)1, 2;
-
0
0.5
V
BST - GATE(H)1,2; Note 2
Low Voltage (AC)
Rise Time
Measure:GATE(L)1,2 or GATE(H)1, 2; Note 2
1.0 V < GATE(L)1,2 < V CC - 1.0 V
-
-
0
20
0.5
50
V
ns
1.0 V < GATE(H)1,2 < BST - 1.0 V,
BST ≤ 14 V
Fall Time
V CC - 1.0 > GATE(L)1,2 > 1.0 V
-
15
50
ns
BST - 1.0 > GATE(H)1,2 > 1.0 V,
BST ≤ 14 V
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE(H)1(2) and GATE(L)1(2) pulldown
GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V
BST ≤ 14 V
GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V;
BST ≤ 14 V
Resistance to GND
20
20
50
40
40
125
70
70
280
ns
ns
k W
Note 2
PWM Comparator
PWM Comparator Offset
V FFB1(2) = 0 V; Increase COMP1,2 until
0.30
0.425
0.55
V
GATE(H)1,2 starts switching
Artificial Ramp
Minimum Pulse Width
Duty cycle = 50%, Note 2
Note 2
40
-
70
-
100
300
mV
ns
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
R OSC Voltage
Phase Difference
R OSC = 61.9 k; Measure GATE(H)1; Note 2
R OSC = 30.9 k; Measure GATE(H)1
R OSC = 15.1 k; Measure GATE(H)1; Note 2
R OSC = 30.9 k, Note 2
-
112
250
450
0.970
-
150
300
600
1.000
180
188
350
750
1.030
-
kHz
kHz
kHz
V
°
2. Guaranteed by design, not 100% tested in production.
http://onsemi.com
4
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