参数资料
| 型号： | NCP5422ADR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP5422ADR2OS |
NCP5422A
where:
T J = FET junction temperature;
T A = ambient temperature;
P HFET(TOTAL) = total switching (upper) FET losses;
R q JA = upper FET junction-to-ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
The IC power dissipation is determined by the formula:
PCONTROL(IC) + ICC1VCC1 ) IBSTVBST ) PGATE(H)1
) PGATE(L)1 ) PGATE(H)2 ) PGATE(L)2
where:
P CONTROL(IC) = control IC power dissipation;
I CC1 = IC quiescent supply current;
V CC1 = IC supply voltage;
P GATE(H) = upper MOSFET gate driver (IC) losses;
PRMS(L) + IRMS2
RDS(ON)
P GATE(L) = lower MOSFET gate driver (IC) losses.
+ [IOUT
(1 * D) ]2
RDS(ON)
The upper (switching) MOSFET gate driver (IC) losses
are:
where:
P RMS(L) = lower MOSFET conduction losses;
I OUT = load current;
D = Duty Cycle;
R DS(ON) = lower FET drain-to-source on-resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non-overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PGATE(H) + QGATE(H) fSW VBST
where:
P GATE(H) = upper MOSFET gate driver (IC) losses;
Q GATE(H) = total upper MOSFET gate charge at V CC ;
f SW = switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
PGATE(L) + QGATE(L) fSW VCC
where:
P GATE(L) = lower MOSFET gate driver (IC) losses;
PSWL + VSD
ILOAD
non-overlap time
fSW
Q GATE(L) = total lower MOSFET gate charge at V CC ;
RSENSE + 0.070 V
where:
P SWL = lower FET switching losses;
V SD = lower FET source-to-drain voltage;
I LOAD = load current;
Non-overlap time = GATE(L)-to-GATE(H) or
GATE(H)-to-GATE(L) delay (from NCP5422A data sheet
Electrical Characteristics section);
f SW = switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL) + PRMS(L) ) PSWL
where:
P LFET(TOTAL) = Synchronous (lower) FET total losses;
P RMS(L) = Switch Conduction Losses;
P SWL = Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
TJ + TA ) [PLFET(TOTAL) R Q JA]
where:
T J = MOSFET junction temperature;
T A = ambient temperature;
P LFET(TOTAL) = total synchronous (lower) FET losses;
R q JA = lower FET junction-to-ambient thermal resistance.
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V CC , and the NCP5422A operating frequency. The
average MOSFET gate charge current typically dominates
f SW = switching frequency;
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Current Sensing
The current supplied to the load can be sensed easily using
the IS+ and IS- pins for the output. These pins sense a
voltage, proportional to the output current, and compare it to
a fixed internal voltage threshold. When the differential
voltage exceeds 70 mV, the internal overcurrent protection
system goes into hiccup mode. Two methods for sensing the
current are available.
Sense Resistor. A sense resistor can be added in series
with the inductor. When the voltage drop across the sense
resistor exceeds the internal voltage threshold of 70 mV, a
fault condition is set.
The sense resistor is selected according to:
ILIMIT
In a high current supply, the sense resistor will be a very
low value, typically less than 10 m W . Such a resistor can be
either a discrete component or a PCB trace. The resistance
value of a discrete component can be more precise than a
PCB trace, but the cost is also greater.
Setting the current limit using an external sense resistor is
very precise because all the values can be designed to
specific tolerances. However, the disadvantage of using a
sense resistor is its additional constant power loss and heat
generation.
the control IC power dissipation.
http://onsemi.com
13
相关PDF资料 |
PDF描述 |
|---|---|
| NCP5424DR2G | IC REG CTRLR BUCK PWM 16-SOIC |
| NCP5425DB | IC REG CTRLR BUCK PWM VM 20TSSOP |
| NCP5501DT50RKG | IC REG LDO 5V .5A DPAK |
| NCP5666DS50R4G | IC REG LDO 5V 3A D2PAK-5 |
| NCP5667DS50R4G | IC REG LDO 5V 3A D2PAK-5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NCP5422ADR2G | 功能描述:DC/DC 开关控制器 Dual Out-Of-Phase Synchronous Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5422EVB | 功能描述:电源管理IC开发工具 ANA SW REG EVAL BRD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| NCP5423 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5423DR2G | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5424 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Synchronous Buck Controller with Input Current Sharing |
发布紧急采购，3分钟左右您将得到回复。