参数资料
| 型号： | NCP5422ADR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP5422ADR2OS |
NCP5422A
Inductor ESR. Another means of sensing current is to use
the intrinsic resistance of the inductor. A model of an
inductor (Figure 9) reveals that the windings of an inductor
have an effective series resistance (ESR).
The voltage drop across the inductor ESR can be
measured with a simple parallel circuit: an RC integrator. If
the value of R S1 and C are chosen such that:
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (V FB ),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
internal slope compensation is insufficient, the performance
of the NCP5422A-based regulator can be improved through
the addition of a fixed amount of external slope
L
ESR
+ RS1C
compensation at the output of the PWM Error Amplifier (the
COMP pin) during the regulator off-time. Referring to
(1 * e t )
VSLOPECOMP + VGATE(L)
then the voltage measured across the capacitor C will be:
VC + ESR ILIM
Selecting Components. Select the capacitor C first. A
value of 0.1 m F is recommended. The value of R S1 can be
selected according to:
Figure 10, the amount of voltage ramp at the COMP pin is
dependent on the gate voltage of the lower (synchronous)
FET and the value of resistor divider formed by R1and R2.
-t
R2
R1 ) R2
RS1 +
1
ESR
C
where:
V SLOPECOMP = amount of slope added;
ILIM + 0.070 V
Typical values for inductor ESR range in the low m W .
Consult manufacturer's datasheet for specific details.
Selection of components at these values will result in a
current limit of:
ESR
V GATE(L) = lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t ON or t OFF (switch off-time);
t = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
V CC
L
ESR
COMP
GATE(H)
RS1
C
Co
C COMP
GATE(L)
NCP5422A
R2
C1
R1
IS+
IS-
Figure 9. Inductor ESR Current Sensing
GATE(L)
To Synchronous
FET
Figure 10. Small RC Filter Provides the
Given an ESR value of 3.5 m W , the current limit becomes
20 A. If an increased current limit is required, a resistor
divider can be added.
The advantages of setting the current limit by using the
winding resistance of the inductor are that efficiency is
maximized and heat generation is minimized. The tolerance
of the inductor ESR must be factored into the design of the
current limit. Finally, one or two more components are
required for this approach than with resistor sensing. Note
that, in the example of Figure 9, the IS+ input bias current
flowing through RS1 will introduce a small offset error. If
RS1 = 4 k W , at the maximum bias current limit of 1 m A, the
error will be 4 mV. This error can be avoided by using two
separate resistors, each half the calculated value, as shown
(R1 through R4) in the typical application circuit of
Figure 1.
Adding External Slope Compensation
Today's voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
Proper Voltage Ramp at the Beginning of
Each On-Time Cycle
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off-time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
http://onsemi.com
14
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| NCP5422ADR2G | 功能描述:DC/DC 开关控制器 Dual Out-Of-Phase Synchronous Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5422EVB | 功能描述:电源管理IC开发工具 ANA SW REG EVAL BRD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| NCP5423 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5423DR2G | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5424 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Synchronous Buck Controller with Input Current Sharing |
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