参数资料
| 型号： | NCP5422ADR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 750kHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP5422ADR2OS |
NCP5422A
ELECTRICAL CHARACTERISTICS (0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; R OSC = 30.9 k, C COMP1,2 = 0.1 m F,
10.8 V < V CC < 13.2 V; 10.8 V < BST < 20 V, C GATE(H)1,2 = C GATE(L)1,2 = 1.0 nF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Supply Currents
V CC Current
BST Current
COMP1,2 = 0 V (No Switching)
COMP1,2 = 0 V (No Switching)
-
-
13
3.5
17
6.0
mA
mA
Undervoltage Lockout
Start Threshold
Stop Threshold
Hysteresis
GATE(H) Switching; COMP1,2 charging
GATE(H) not switching; COMP1,2 discharging
Start-Stop
7.8
7.0
0.5
8.6
7.8
0.8
9.4
8.6
1.5
V
V
V
Hiccup Mode Overcurrent Protection
OVC Comparator Offset Voltage
Discharge Threshold
IS+ 1(2) Bias Current
IS- 1(2) Bias Current
OVC Common Mode Range
OVC Latch COMP1 Discharge Current
OVC Latch COMP2 Discharge Current
COMP1 Charge/Discharge Ratio in OVC
0 V < IS+ 1(2) < 5.5 V, 0 V < IS- 1(2) < 5.5 V
-
0 V < IS+ 1(2) < 5.5 V
0 V < IS- 1(2) < 5.5 V
Note 3
COMP1 = 1.0 V
COMP2 = 1.0 V
-
55
0.20
-1.0
-1.0
0
2.0
0.3
5.0
70
0.25
0.1
0.1
-
5.0
1.2
6.0
85
0.30
1.0
1.0
5.5
8.0
3.5
7.0
mV
V
m A
m A
V
m A
mA
-
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN SYMBOL
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS-1
V FB1
COMP1
COMP2
V FB2
IS-2
IS+2
R OSC
V CC
GATE(L)2
GATE(H)2
FUNCTION
High Side Switch FET driver pin for channel 1.
Low Side Synchronous FET driver pin for channel 1.
Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
Power input for GATE(H)1 and GATE(H)2 pins.
Positive input for channel 1 overcurrent comparator.
Negative input for channel 1 overcurrent comparator.
Error amplifier inverting input for channel 1.
Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation. The same capacitor provides Soft-Start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.3 V.
Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation and Soft-Start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.3 V.
Error amplifier inverting input for channel 2.
Negative input for channel 2 overcurrent comparator.
Positive input for channel 2 overcurrent comparator.
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
Input Power supply pin.
Low Side Synchronous FET driver pin for channel 2.
High Side Switch FET driver pin for channel 2.
http://onsemi.com
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