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| 型号： | NCV8855BMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG QD BUCK/LINEAR 40QFN |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）（2），线性（LDO）（2） |
| 功能： | 汽车无线电设备和仪表板电源 |
| 输出数： | 4 |
| 频率 - 开关： | 170kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 可调式，2.5A |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 是 |
| 电源电压： | 9 V ~ 18 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 标准包装 |
| 其它名称： | NCV8855BMNR2GOSDKR |
NCV8855
when designing the thermal solution. The IPAK package can
be attached to the radio’s metal enclosure or it can be
attached to an independent heatsink. If output current
demands are low, then a DPAK package can be used for a
surface mount solution.
LDO Output Capacitor Selection
The LDO controllers have been optimize and
compensated to work with a variety of output capacitors.
Aluminum electrolytic capacitors with an ESR up to 5 W to
ceramic capacitors with an ESR down to 10 m W can be used.
Depending on load requirements, the output capacitor can
range from 10 m F to as much as 100 m F. There are many
capacitor vendors which supply automotive rated parts that
fall within these ranges. For example, the Nichicon UD or
PM type capacitors are suited well for the LDO controllers
and automotive radio application. Values outside of these
ranges can be used, but may require external compensation.
For the DRV_VPP supply, a local bypass capacitor is not
only required for stability, but also to reduce noise and
supply peak currents during operation. Use a 1 to 4.7 m F, low
ESR capacitor. Multilayer ceramic chip (MLCC) capacitors
provide the best combination of low ESR and small size.
This capacitor must be referenced to PGND. The bootstrap
circuit comprises a charge storage capacitor (C BST1 ) and the
internal bootstrap diode. Typical C BST1 values range from
100 nF to 1 m F. The average forward current can be
estimated by the following equation:
I BST1 + Q GATE FSW (eq. 6)
where, Q GATE is the total gate charge. The average
forward current through the internal diode should not exceed
its rated maximum of 12 mA. This puts a limitation on the
MOSFETs used at a particular switching frequency.
The power dissipation for the internal MOSFET drivers
can be calculated using the following equation:
SMPS1 MOSFET Selection
Pd SMPS1_drv + Pd GH1_drv ) Pd GL1_drv
(eq. 7)
SMPS1 has integrated MOSFET drivers optimized for
driving N ? channel MOSFETs in a synchronous buck
Pd GH1_drv + Q GH1
V GH1
FSW
(eq. 8)
(eq. 9)
configuration. The lower MOSFET driver is designed to
drive a ground ? referenced low R DS(on) n ? channel
MOSFET. The supply rail for the lower driver is internally
connected to DRV_VPP and the PGND pin is it’s ground
reference. The upper MOSFET driver is a floating gate
driver designed to drive low R DS(on) n ? channel MOSFETs.
A bootstrap circuit referenced to SN1 as shown in figure 1
develops the supply rail for the upper MOSFET driver.
The driver circuitry includes non ? overlap protection. The
non ? overlap protection prevents both Q1 (upper MOSFET)
and Q2 (lower MOSFET) from being on at the same time,
and minimizes the associated off times.
This helps reduce power losses in the switching elements.
The non ? overlap protection circuit accomplishes this by
controlling the delay from Q1’s turn ? off to Q2’s turn ? on,
and from Q2’s turn ? off to Q1’s turn on by monitoring the
voltage at the SN1 and GL1 pins. When the internal PWM
signal goes low, GH1 will go low, turning Q1 off. However,
before Q2 can turn on, the non ? overlap protection circuit
waits for the voltage at the SN1 pin to fall below 1.8 V. Once
SN1 falls below the 1.8 V threshold, GL1 will go high,
turning Q2 on. However, if SN1 does not fall below 1 V in
100 ns, the safety timer circuit will override the normal
control scheme and drive GL1 high. This will help insure
that if Q1 fails to turn off it will not produce an over ? voltage
at the output.
Similarly, to prevent cross conduction during Q2’s
turn ? off and Q1’s turn ? on, the non ? overlap circuit monitors
the voltage at the gate of Q2 through the GL1 pin. When the
internal PWM signal goes high, GL1 will go low turning Q2
off. However, before Q1 can turn on, the non ? overlap
protection circuit waits for the voltage at GL1 to drop below
2
Pd GL1_drv + C GL1 V GL1 FSW
where, Q GH1 is the total gate charge of the upper
MOSFET, C GL1 is the total input capacitance of the lower
MOSFET, V GH1 = V GL1 = 7.2 V (typ.) which is the
DRV_VPP output voltage.
One method to improve the IC power dissipation is to
diode ? or the 8 V SMPS output to the DRV_VPP pin. This
will override the internal regulator and the IC will run from
the SMPS output. Doing this will incrementally increase the
gate drivers power dissipation, but will reduce the loss
associated with the DRV_VPP running from battery.
For example, if the DRV_VPP is operating at 12 mA from
a 14.4 V battery to power SMPS1’s gate driver circuit, the
power dissipation from this will be 90 mW. In addition, with
a 20 nC GH1 change and a 1.8 nF GL1 capacitance, the gate
driver loss will be 80 mW. This is a total of 170 mW of power
dissipation due to running the gate drivers at 340 kHz.
However, if there was a diode ? or to the DRV_VPP from the
8 V output of one of the SMPSs, then the DRV_VPP LDO
losses are eliminated, and the total power dissipation from
running the SMPS1 gate drivers reduce to 95 mW. The
improvement gets better when accounting for SMPS2’s gate
driver loss. This savings can prove to be beneficial in fast
FSW and high current applications.
There are two recommended n ? channel MOSFET for
SMPS1, the NTD24N06, which has a 60 V max VDS, and
the NTD5407N, which has a 40 V max VDS. Determining
which MOSFET to use is predicated by the load dump
requirements. The same device can be used for the upper and
lower MOSFET. The benefit of this is reduced cost due to
economies of scale.
2 V. Once this has occurred, GH1 will go high, turning Q1
on.
http://onsemi.com
18
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NCV8855BMNR2GEVB | 功能描述:电源管理IC开发工具 SMPS ASIC RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| NCV8870 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Automotive Grade Non-Synchronous Boost Controller |
| NCV887000 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Automotive Grade Non-Synchronous Boost Controller |
| NCV887000D1R2G | 功能描述:低压差稳压器 - LDO Auto Grade Non-Sync Boost Controller RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| NCV887001 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Automotive Grade Non-Synchronous Boost Controller |
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