参数资料
型号: NCV8855BMNR2G
厂商: ON Semiconductor
文件页数: 21/24页
文件大小: 0K
描述: IC REG QD BUCK/LINEAR 40QFN
标准包装: 1
拓扑: 降压(降压)(2),线性(LDO)(2)
功能: 汽车无线电设备和仪表板电源
输出数: 4
频率 - 开关: 170kHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 可调式,2.5A
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 9 V ~ 18 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 标准包装
其它名称: NCV8855BMNR2GOSDKR
NCV8855
control loop has a gain crossing with ? 20 dB/decade slope
and a phase margin greater than 45 ° .
gain = 0 dB or a gain of 1. In the plot above, the UGB is the
point where the red line crosses the W axis. Goal 2 is to have
the closed loop gain cross 0 dB with a ? 20 dB/decade slope
dB
w Z1 +
1
R 2 @ C 2
w Z2 +
1
R 1 ) R 3 @ C 3
1
w P1 +
C 1 @ C 2
C 1 ) C 2
w P2 +
1
R 3 @ C 3
also known as a ? 1 slope. Goal 3 is to achieve over 45 ° of
phase margin when the gain crosses 0 dB.
These are just goals. Sometimes the crossover frequency
is reduced below 1/10 FSW in order to meet goal 3.
Conversely, some designs will push the crossover frequency
as high as it can (as long as it is below 1/2 FSW) with a
reduce phase margin of 30 ° in order to get a faster transient
response. The only two absolutes are that the crossover
frequency cannot exceed 1/2 FSW and the phase margin has
w
to be greater than 0 ° at crossover. However, a SMPS
operating towards these absolutes will experience sever
ringing before it dampens out.
1
w LC +
L OUT @ C OUT
1
w ESR +
ESR @ C OUT
Error Amplifier
Compensation Network
Modulator Gain
Closed Loop Gain
To achieve the above goals, the following guidelines
should be adopted.
? Place wZ1 at half the resonance of wLC
? Place wZ2 at or around wLC
? Place wP1 at wESR
Figure 27.
To reiterate, there are 3 primary goals to compensating.
Goal 1 is to have a high a unity gain bandwidth (UGB) that
is greater than 1/10 the switching frequency, but less than 1/2
the switching frequency. UGB is also known as the
crossover frequency. This is the point where the closed loop
? Place wP2 at half the switching frequency
Performing these calculations will take some amount of
iterations and bench testing to verify results. However,
ON Semiconductor has developed a tool to speed up the
design process tremendously with great ease and accuracy.
This tool can be downloaded by following the below link.
http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP
http://onsemi.com
21
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