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参数资料
| 型号： | NT1GT64U8HA0B-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 2/20页 |
| 文件大小： | 311K |
| 代理商： | NT1GT64U8HA0B-3C |
NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green)
NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green)
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1
10
03/2005
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2 (1GB)
128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Note
Byte
Description
DDR2
-400
(-5A)
DDR2
-533
(-37B)
DDR2
-667
(-3C)
DDR2
-400
(-5A)
DDR2
-533
(-37B)
DDR2
-667
(-3C)
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
DDR2-SDRAM
08
3
Number of Row Addresses on Assembly
14
0E
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank, Package, and Height
2 rank, Height=30mm
61
6
Data Width of this Assembly
X64
40
7
Reserved
Undefined
00
8
Voltage Interface Level of this Assembly
SSTL_1.8V
05
9
DDR2 SDRAM Device Cycle Time at Maximum Support
CAS Latency CL=5
5ns
3.75ns
3ns
50
3D
30
10
DDR2 SDRAM Device Access Time (tac) from Clock at
CL=5
0.6ns
0.5ns
0.45ns
60
50
45
11
DIMM Configuration Type
Non - ECC
00
12
Refresh Rate/Type
7.8s/self
82
13
Primary DDRII SDRAM Width
X8
08
14
Error Checking DDRII SDRAM Device Width
N/A
00
15
Reserved
Undefined
00
16
DDR2 SDRAM Device Attributes: Burst Length Supported
4,8
0C
17
DDR2 SDRAM Device Attributes: Number of Device Banks
4
04
18
DDR2 SDRAM Device Attributes: CAS Latencies Supported
3/4/5
38
19
Reserved
Undefined
00
20
DDR2 SDRAM DIMM Type Information
Regular UDIMM (133.35mm)
02
21
DDR2 SDRAM Module Attributes:
Normal DIMM
00
22
DDR2 SDRAM Device Attributes: General
Support weak driver
01
13
23
Minimum Clock Cycle at CL=4
5ns
3.7ns
3.75ns
50
3D
24
Maximum Data Access Time (tac) from Clock at CL=4
0.6ns
0.5ns
60
50
25
Minimum Clock Cycle Time at CL=3
5ns
50
26
Maximum Data Access Time (tac) from Clock at CL=3
0.6ns
60
27
Minimum Row Precharge Time (tRP)
15ns
3C
28
Minimum Row Active to Row Active delay (tRRD)
7.5ns
1E
29
Minimum RAS to CAS delay (tRCD)
15ns
3C
30
Minimum Active to Precharge Time (tRAS)
45ns
2D
31
Module Bank Density
512MB
80
32
Address and Command Input Setup Time Before Clock (tIS)
0.35ns
0.25ns
0.2ns
35
25
20
33
Address and Command Input Hold Time After Clock (tIH)
0.475ns 0.375ns 0.325ns
47
37
32
34
Data Input Setup Time Before Clock (tDS)
0.15ns
0.1ns
0.05ns
15
10
05
35
Data Input Hold Time After Clock (tDH)
0.275ns 0.225ns 0.175ns
27
22
17
36
Write Recovery Time (tWR)
15ns
3C
37
Internal Write to Read Command delay (tWTR)
10ns
7.5ns
28
1E
38
Internal Read to Precharge Command delay (tRTP)
7.5ns
1E
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