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参数资料
| 型号： | NT1GT64U8HA0B-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 6/20页 |
| 文件大小： | 311K |
| 代理商： | NT1GT64U8HA0B-3C |
NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green)
NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green)
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1
14
03/2005
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
TA = 0 °C ~ 70 °C; VDDQ = VDD = 1.8V ± 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-3200
(-5A)
PC2-4200
(-37B)
PC2-5300
(-3C)
Unit
Notes
I DD0
Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
450
520
TBD
mA
1, 2
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC
(MIN);
CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs
changing once per clock cycle
480
600
TBD
mA
1, 2
I DD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE
≤ VIL (MAX); tCK = tCK (MIN)
30
TBD
mA
1, 2
I DD2N
Idle Standby Current: CS
≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK =
tCK (MIN); address and control inputs changing once per clock cycle
260
320
TBD
mA
1, 2
I DD3P
Active Power-Down Standby Current: one bank active; power-down
mode; CKE
≤ VIL (MAX); tCK = tCK (MIN)
100
130
TBD
mA
1, 2
I DD3N
Active Standby Current: one bank; active/precharge; CS
≥ VIH (MIN); CKE
≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs changing
once per clock cycle
280
320
TBD
mA
1, 2
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT =
0mA
565
720
TBD
mA
1, 2
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN)
600
760
TBD
mA
1, 2
I DD5
Auto-Refresh Current: tRC = tRFC (MIN)
965
1050
TBD
mA
1, 2
I DD6
Self-Refresh Current: CKE
≤ 0.2V
32
TBD
mA
1, 2
I DD7
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; tRC = tRC (min); IOUT = 0mA.
1050
1110
TBD
mA
1, 2
Note:
1.
VDDQ=1.8V ± 0.1V, VDD=1.8V ± 0.1V
2.
I DD specifications are tested after the device is properly initialized and ODT disabled.
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