- 您现在的位置：买卖IC网 > PDF目录189449 > OR4E042BM416-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 380000 GATES, PBGA416 PDF资料下载
参数资料
| 型号： | OR4E042BM416-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封装： | PLASTIC, FBGA-416 |
| 文件页数： | 115/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E042BM416-DB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页当前第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页
66
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA Conguration Modes (continued)
One master mode FPGA can interface to the memory
and provide conguration data on DOUT to additional
FPGAs in a daisy-chain. The conguration data on
DOUT is provided synchronously with the rising edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
Master Serial Mode
In the master serial mode, the FPGA loads the congu-
ration data from an external serial ROM. The congura-
tion data is either loaded automatically at start-up or on
a PRGM command to recongure. Serial PROMs can
be used to congure the FPGA in the master serial
mode.
Conguration in the master serial mode can be done at
powerup and/or upon a congure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET
/OE and CE inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be congured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a congure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple conguration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the CLK
input of the serial ROM. During the conguration pro-
cess, CCLK clocks one data bit on each rising edge.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the RESET/OE and CE of the serial
ROM(s). There are several methods for enabling the
serial ROM’s RESET/OE and CE inputs. The serial
ROM’s RESET/OE is programmable to function with
RESET active-high and OE active-low or RESET active-
low and OE active-high.
In Figure 39, serial ROMs are cascaded to congure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's PRGM input. The
FPGA’s INIT input is connected to the serial ROMs’
RESET
/OE input, which has been programmed to
function with RESET active-low and OE active-high.
The FPGA DONE is routed to the CE pin. The low on
DONE enables the serial ROMs. At the completion of
conguration, the high on the FPGAs DONE disables
the serial ROM.
Serial ROMs can also be cascaded to support the con-
guration of multiple FPGAs or to load a single FPGA
when conguration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the rst serial ROM is read, the serial ROM outputs
CEO
low and 3-states the DATA output. The next serial
ROM recognizes the low on CE input and outputs con-
guration data on the DATA output. After conguration
is complete, the FPGA’s DONE output into CE disables
the serial ROMs.
This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple congura-
tion programs. In these applications, the next
conguration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous conguration program. The reason the interface in
Figure 39 will not work in this application is that the low
output on the INIT signal would reset the serial ROM
address pointer, causing the rst conguration to be
reloaded.
In some applications, there can be contention on the
FPGA's DIN pin. During conguration, DIN receives
conguration data, and after conguration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in ORCA Foundry) may correct the problem.
An alternative is to use LDC to drive the serial ROM's
CE
pin. In order to reduce noise, it is generally better to
run the master serial conguration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
One FPGA in master serial mode can provide congu-
ration data out on DOUT to additional FPGAs in a
daisy-chain conguration. The conguration data on
DOUT is provided synchronously with the rising edge
of CCLK.
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E043BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E043BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E043BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E061BA352-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA352 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-2BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-3BA352C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-3BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。