参数资料
型号: OR4E042BM416-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA416
封装: PLASTIC, FBGA-416
文件页数: 119/151页
文件大小: 2680K
代理商: OR4E042BM416-DB
Lattice Semiconductor
7
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4-, 5-, or
6-input logic function and many multilevel logic func-
tions using ORCA’s SWL connections. In ripple mode,
the high-speed carry logic is used for arithmetic func-
tions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32x4 synchronous read/write or ROM, in either single-
or dual-port mode.
The SLIC is connected from PLC routing resources
and from the outputs of the PFU. It contains eight
3-state, bidirectional buffers and logic to perform up to
a 10-bit AND function for decoding, or an AND-OR with
optional INVERT to perform PAL-like functions. The
3-state drivers in the SLIC and their direct connections
from the PFU outputs make fast, True 3-state buses
possible within the FPGA.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 53 exter-
nal inputs and 20 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses 36 data input lines for the LUTs, eight
data input lines for the latches/FFs, eight control inputs
(CLK[1:0], CE[1:0], LSR[1:0], SEL[1:0]), and a carry
input (CIN) for fast arithmetic functions and general-
purpose data input for the ninth FF. There are eight
combinatorial data outputs (one from each LUT), eight
latched/registered outputs (one from each latch/FF), a
carry-out (COUT), and a registered carry-out (REG-
COUT) that comes from the ninth FF. The carry-out sig-
nals are used principally for fast arithmetic functions.
There are also two dedicated F6 mode outputs which
are for the 6-input LUT function and 8 to 1 MUX.
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The eight
sets of LUT inputs are labeled as K0 through K7 with
each of the four inputs to each LUT having a sufx
of _x, where x is a number from 0 to 3.
There are four F5 inputs labeled A through D. These
are used for additional LUT inputs for 5- and 6-input
LUTs or as a selector for multiplexing two 4-input LUTs.
Four adjacent LUT4s can also be multiplexed together
with a 4 to 1 MUX to create a 6-input LUT. The eight
direct data inputs to the latches/FFs are labeled as
DIN[7:0]. Registered LUT outputs are shown as Q[7:0],
and combinatorial LUT outputs are labeled as F[7:0].
The PFU implements combinatorial logic in the LUTs
and sequential logic in the latches/FFs. The LUTs are
static random access memory (SRAM) and can be
used for read/write or ROM.
Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combina-
torial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which
reduces the delay out of the PFU. It is possible to use
the LUTs and latches/FFs more or less independently,
allowing, for instance, a comparator function in the
LUTs simultaneously with a shift register in the FFs.
相关PDF资料
PDF描述
OR4E042BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E043BA352-DB FPGA, 1296 CLBS, 380000 GATES, PBGA352
OR4E043BM416-DB FPGA, 1296 CLBS, 380000 GATES, PBGA416
OR4E043BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E061BA352-DB FPGA, 2024 CLBS, 515000 GATES, PBGA352
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