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| 型号： | OR4E043BM416-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封装： | PLASTIC, FBGA-416 |
| 文件页数： | 107/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E043BM416-DB |
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Lattice Semiconductor
59
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA States of Operation (continued)
There are conguration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 35 shows the start-up timing for ORCA
FPGAs. The system designer determines the relative
timing of the I/Os becoming active, DONE going high,
and the release of the set/reset of internal FFs. In the
ORCA Series FPGA, the three events can occur in any
arbitrary sequence. This means that they can occur
before or after each other, or they can occur simulta-
neously.
There are four main start-up modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.
The only difference between the modes starting with
CCLK and those starting with UCLK is that for the
UCLK modes, a user clock must be supplied to the
start-up logic. The timing of start-up events is then
based upon this user clock, rather than CCLK. The dif-
ference between the SYNC and NOSYNC modes is
that for SYNC mode, the timing of two of the start-up
events, release of the set/reset of internal FFs, and the
I/Os becoming active is triggered by the rise of the
external DONE pin followed by a variable number of
rising clock edges (either CCLK or UCLK). For the
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.
DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing. The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
as an active-high ready signal, an active-low PROM
enable, or a reset to other portions of the system.
When used in SYNC mode, these ANDed DONE pins
can be used to synchronize the other two start-up
events, since they can all be synchronized to the same
external signal. This signal will not rise until all FPGAs
release their DONE pins, allowing the signal to be
pulled high.
An example of using the synchronized modes are the
CCLK_SYNC synchronized start-up mode where
DONE is released on the rst CCLK rising edge, C1
(see Figure 35).
Since this is a synchronized start-up mode, the open-
drain DONE signal can be held low externally to stop
the occurrence of the other two start-up events. Once
the DONE pin has been released and pulled up to a
high level, the other two start-up events can be pro-
grammed individually to either happen immediately or
after up to four rising edges of CCLK (Di, Di + 1, Di + 2,
Di + 3, Di + 4). The default is for both events to happen
immediately after DONE is released and pulled high.
A commonly used design technique is to release
DONE one or more clock cycles before allowing the I/O
to become active. This allows other conguration
devices, such as PROMs, to be disconnected using the
DONE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations, and maintaining I/Os as
3-stated outputs until contentions are resolved.
Each of these start-up options can be selected during
bit stream generation in ORCA Foundry, using
Advanced Options. For more information, please see
the ORCA Foundry documentation.
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E043BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E061BA352-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA352 |
| OR4E061BM680-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA680 |
| OR4E062BA352-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA352 |
| OR4E062BM680-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA680 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-3BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E06-1BA352C | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06-1BA352I | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06-1BM680C | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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