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参数资料
型号： OR4E043BM416-DB
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封装： PLASTIC, FBGA-416
文件页数： 81/151页
文件大小： 2680K
代理商： OR4E043BM416-DB
Lattice Semiconductor
35
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Inputs
There are many major options on the PIO inputs that
can be selected in the ORCA Foundry tools listed in
Table 14. Inputs may have a pull-up or pull-down resis-
tor selected on an input for signal stabilization and
power management. Input signals in a PIO are passed
to CIB routing and/or a fast route into the clock routing
system. A fast input from one PIO per PIC is also avail-
able to drive the edge clock network for fast I/O timing
to other nearby PIOs.
There is also a programmable delay available on the
input. When enabled, this delay affects the INFF and
INDD signals of each PIO, but not the clock input. The
delay allows any signal to have a guaranteed zero hold
time when input.
Inputs should have transition times of less than 100 ns
and should not be left oating. For full swing inputs, the
timing characterization is done for rise/fall times of
≥ 1 V/ns. If any pin is not used, it is 3-stated with an
internal pull-up resistor enabled automatically after
conguration. Floating inputs increase power con-
sumption, produce oscillations, and increase system
noise. The inputs in LVTTL, LVCMOS2, and
LVCMOS18 modes have a typical hysteresis of approx-
imately 250 mV to reduce sensitivity to input noise. The
PIC contains input circuitry which provides protection
against latch-up and electrostatic discharge.
The other features of the PIO inputs relate to the latch/
FF structure in the input path. In latch mode, the input
signal is fed to a latch that is clocked by either the pri-
mary, secondary, or edge clock signal. The clock may
be inverted or noninverted. There is also a local set/
reset signal to the latch. The senses of these signals
are also programmable as well as the capability to
enable or disable the global set/reset signal and select
the set/reset priority. The same control signals may
also be used to control the input latch/FF when it is
congured as a FF instead of a latch, with the addition
of another control signal used as a clock enable. The
PIOs are paired together and have independent CE,
Set/reset, and GSRN control signals per PIO pair.
There are two options for zero-hold input capture in the
PIO. If input delay mode is selected to delay the signal
from the input pin, data can be either registered or
latched with guaranteed zero-hold time in the PIO
using a global primary system clock. The fast zero-hold
mode of the PIO input takes advantage of a latch/FF
combination to latch the data quickly for zero-hold
using a fast edge clock before passing the data to the
FF which is clocked by a global primary system clock.
The combination of input register capability with non-
registered inputs provides for input signal demultiplex-
ing without any additional resources. The PIO input
signal is sent to both the input register and directly to
the unregistered input (INDD). The signal is latched
and output to routing at INFF. These signals may then
be registered or otherwise processed in the PLCs.
Every PIO input can also perform input double data
rate (DDR) functions with no PLC resources required.
This type of scheme is necessary for DDR applications
which require data to be clocked in from the I/O on both
edges of the clock. In this scheme the input of INFF
and INSH are captured on the positive and negative
edges of the clock.
Table 14. PIO Options
Input
Option
InputSpeed
Fast,Delayed,Normal
FloatValue
Pull-up,Pull-down,None
RegisterMode
Latch,FF,FastZeroHoldFF,
None(directinput)
ClockSense
Inverted,Noninverted
KeeperMode
on,off
LVDSResistor
on,off
Output
Option
OutputSpeed
Fast,Slew
OutputDrive
Current
12mA/6mA,6mA/3mA,or
24mA/12mA
OutputFunction
Normal,FastOpenDrain
OutputSense
Active-high,Active-low
3-StateSense
Active-high,Active-low
ClockSense
Inverted,Noninverted
Logic Options
See Table 15
I/OControls
Option
ClockEnable
Active-high,Active-low,
AlwaysEnabled
Set/ResetLevel
Active-high,Active-low,
NoLocalReset
Set/ResetType
Synchronous,Asynchronous
Set/ResetPriority
CEoverLSR,LSRoverCE
GSRControl
EnableGSR,DisableGSR
相关PDF资料
PDF描述
OR4E043BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
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