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参数资料
型号： OR4E043BM416-DB
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封装： PLASTIC, FBGA-416
文件页数： 82/151页
文件大小： 2680K
代理商： OR4E043BM416-DB
36
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Outputs
The PIO’s output drivers have programmable drive
capability and slew rates. Two propagation delays (fast,
slewlim) are available on output drivers. There are
three combinations of programmable drive currents
(24 mA sink/12 mA source, 12 mA sink/6 mA source,
and 6 mA sink/3 mA source). At powerup, the output
drivers are in slewlim mode with 12mA sink/6 mA
source. If an output is not to be driven in the selected
conguration mode, it is 3-stated with a pullup resistor.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there
is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1.
Every PIO output can perform output data multiplexing
with no PLC resources required. This type of scheme is
necessary for DDR applications which require data
clocking out of the I/O on both edges of the clock. In
this scheme the OUTFF and OUTSH are registered
and sent out on both the positive and negative edges of
the clock using an output multiplexor. This multiplexor
is controlled by either the edge clock or system clock.
This multiplexor can also be congured to select
between one registered output from OUTFF and one
nonregistered output from OUTDD.
The PIC logic block can also generate logic functions
based on the signals on the OUTDD and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 15 is provided as a summary
of the PIO logic options.
Table 15.
PIOLogicOptions
PIO Register Control Signals
The PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and GSRN controls. Table
16 provides a summary of these control signals and
their effect on the PIO latches/FFs. Note that all control
signals are optionally invertible.
Table 16. PIO Register Control Signals
Option
Description
AND
OutputlogicalANDofsignalsonOUTDD
andclock.
NAND
OutputlogicalNANDofsignalsonOUTDD
andclock.
OR
OutputlogicalORofsignalsonOUTDD
andclock.
NOR
OutputlogicalNORofsignalsonOUTDD
andclock.
XOR
OutputlogicalXORofsignalsonOUTDD
andclock.
XNOR OutputlogicalXNORofsignalsonOUTDD
andclock.
Control
Signal
Effect/Functionality
EdgeClock
(ECLK)
Clocksinputfast-capturelatch;option-
allyclocksoutputFF,or
3-stateFF,orPIOshiftregisters.
System
Clock
(SCLK)
Clocksinputlatch/FF;optionallyclocks
outputFF,or3-stateFF,orPIOshift
registers.
Clock
Enable(CE)
Optionallyenables/disablesinputFF
(notavailableforinputlatchmode);
optionallyenables/disablesoutputFF;
separateCEinversioncapabilityfor
inputandoutput.
LocalSet/
Reset(LSR)
Optiontodisable;affectsinputlatch/FF,
outputFF,and3-stateFFifenabled.
GlobalSet/
Reset
(GSRN)
OptiontoenableordisableperPIO
afterinitialconfiguration.
Set/Reset
Mode
Theinputlatch/FF,outputFF,and3-
stateFFareindividuallysetorresetby
boththeLSRandGSRNinputs.
相关PDF资料
PDF描述
OR4E043BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
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