收藏本站
参数资料
型号： OR4E043BM416-DB
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封装： PLASTIC, FBGA-416
文件页数： 85/151页
文件大小： 2680K
代理商： OR4E043BM416-DB
Data Sheet
September, 2002
Lattice Semiconductor
39
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
0204(F).
Figure 24. PIO Shift Register
INDD
OUTSH
OUTDD
PIO
INDD
OUTSH
OUTDD
PIO
INDD
OUTSH
OUTDD
PIO
INDD
OUTSH
OUTDD
PIO
SHIFT REGISTER
OUT FROM FPGA
SHIFT REGISTER
INTO FPGA
CLK
OUTSH1
OUTSH2
OUTSH3
OUTSH4
INSH1
INTSH2
INSH3
INSH4
Special Function Blocks
Special function blocks in the Series 4 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners and MIDs (middle inter-
quad areas) of the FPGA array.
Internal Oscillator
The internal oscillator resides in the upper left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for conguration. It
may also be used after conguration as a general-
purpose clock signal.
Global Set/Reset (GSRN)
The GSRN logic resides in the upper-left corner of the
FPGA. GSRN is an invertible, default, active-low signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during conguration of the device.
The timing of the release of GSRN at the end of cong-
uration can be programmed in the start-up logic
described below. Following conguration, GSRN may
be connected to the RESET pin via dedicated routing, or
it may be connected to any signal via normal routing.
GSRN can also be controlled via a system bus register
command. Within each PFU and PIO, individual FFs
and latches can be programmed to either be set or
reset when GSRN is asserted. Series 4 allows individ-
ual PFUs and PIOs to turn off the GSRN signal to its
latches/FFs after conguration.
The RESET input pad has a special relationship to
GSRN. During conguration, the RESET input pad
always initiates a conguration abort, as described in
the FPGA States of Operation section. After congura-
tion, the GSRN can either be disabled (the default),
directly connected to the RESET input pad, or sourced
by a lower-right corner signal. If the RESET input pad is
not used as a global reset after conguration, this pad
can be used as a normal input pad.
相关PDF资料
PDF描述
OR4E043BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E061BA352-DB FPGA, 2024 CLBS, 515000 GATES, PBGA352
OR4E061BM680-DB FPGA, 2024 CLBS, 515000 GATES, PBGA680
OR4E062BA352-DB FPGA, 2024 CLBS, 515000 GATES, PBGA352
OR4E062BM680-DB FPGA, 2024 CLBS, 515000 GATES, PBGA680
相关代理商/技术参数
参数描述
OR4E04-3BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E06 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E06-1BA352C 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E06-1BA352I 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E06-1BM680C 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*