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| 型号： | OR4E043BM416-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封装： | PLASTIC, FBGA-416 |
| 文件页数： | 89/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E043BM416-DB |
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42
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Special Function Blocks (continued)
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 25, the con-
nections between U1 and U2 (shown by nets a, b,
and c) can be tested by driving a value onto the given
nets from one device and then determining whether
this same value is seen at the other device. This is
determined by shifting 3 bits of data for each pin (one
for the output value, one for captured input value, and
one for the 3-state value) through a boundary scan reg-
ister (BSR) until each one aligns to the appropriate pin.
Then, based upon the value of the 3-state data bit for
each pin, either the I/O pad is driven to the value given
in the output register of the BSR, or an input signal is
applied at the pin. In either case, the BSR input register
is updated with the input value from the I/O pad, which
allows it to be shifted out TDO. Typically, the user will
use the PRELOAD instruction to shift in the rst test
stimulus for the EXTEST instruction. Note that Series 4
boundary scan includes the ability to perform a self-
monitor on each I/O pin by driving out a value from the
output register and checking for this value at the input
register of the same I/O pad.
The SAMPLE instruction is useful for system debug-
ging and fault diagnosis by allowing the data at the
FPGA’s I/Os to be observed during normal operation.
The data for all of the I/Os is captured simultaneously
into the BSR, allowing them to be shifted-out TDO to
the test host. Since each I/O buffer in the PIOs is bidi-
rectional, two pieces of data are captured for each I/O
pad: the value at the I/O pad and the value of the 3-
state control signal.
The PRELOAD instruction is used to allow the scan-
ning of the boundary-scan register without causing
interference to the normal operation of the on-chip sys-
tem logic. In turn it allows an initial data pattern to be
placed at the latched parallel outputs of BSR prior to
selection of another boundary scan test operation. For
example, prior to selection of the EXTEST instruction,
data can be loaded onto the latched parallel outputs
using PRELOAD. As soon as the EXTEST instruction
has been transferred to the parallel output of the
instruction register, the preloaded data is driven
through the system output pins. This ensures that
known data, consistent at the board level, is driven
immediately when the EXTEST instruction is entered.
Without PRELOAD, indeterminate data would be
driven until the rst scan sequence had been com-
pleted.
There are six ORCA-dened instructions. The PLC
scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user-
dened internal scan paths using the PLC latches/FFs
and routing interface. The RAM_Write Enable
(RAM_W) instruction allows the user to serially cong-
ure the FPGA through TDI. The RAM_Read Enable
(RAM_R) allows the user to read back RAM contents
on TDO after conguration. The IDCODE instruction
allows the user to capture a 32-bit identication code
that is unique to each device and serially output it at
TDO. The IDCODE format is shown in Table 19.
An optional IEEE 1149.3 instruction RUNBIST has
been implemented. This instruction is used to invoke
the built in self test (BIST) of regular structures like
RAMs, ROMs, FIFOs, etc., and the surrounding ran-
dom logic in the circuit.
The USERCODE instruction shifts out a 32-bit ID seri-
ally at TDO. At powerup, a default value of the IDCODE
with the manufacturer eld (11-bits) set to all zeros is
loaded. The user can set this 11-bit value to a user-
dened number during device conguration. It may
also be changed by the ISC_PROGRAM_USERCODE
instruction, described later.
Also implemented in Series 4 devices is the IEEE
1532/D1 standards for in-system conguration for pro-
grammable logic devices. Included are 4 mandatory
and 2 optional instructions dened in the standards.
ISC_ENABLE, ISC_PROGRAM, ISC_NOOP, and
ISC_DISABLE are the four mandatory instructions.
ISC_ENABLE initializes the devices for all subsequent
ISC instructions. The ISC_PROGRAM instruction is
similar to the RAM_WRITE instruction implemented in
all ORCA devices where the user must monitor the
PINITN pin for a high indicating the end of initialization
and a successful conguration can be started. The
ISC_PROGRAM instruction is used to program the
conguration memory through a dedicated ISC_Pdata
register. The ISC_NOOP instruction is user when pro-
gramming multiple devices in parallel. During this mode
TDI and TDO behave like BYPASS. The data shifted
through TDI is shifted out through TDO. However the
output pins remain in control of the BSR unlike
BYPASS where they are driven by the system logic.
The ISC_DISABLE is used upon completion of the ISC
programming. No new ISC instructions will be operable
without another ISC_ENABLE instruction.
Optional 1532/D1 instructions include
ISC_PROGRAM_USERCODE. When this instruction is
loaded, the user shifts all 32-bits of a user-dened ID
(LSB rst) through TDI. This overwrites any ID previ-
ously loaded into the ID register. This ID can then be
read back through the USERCODE instruction dened
in IEEE 1149.2.
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| OR4E061BA352-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA352 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-3BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E06-1BA352C | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06-1BA352I | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06-1BM680C | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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