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| 型号： | OR4E043BM416-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封装： | PLASTIC, FBGA-416 |
| 文件页数： | 95/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E043BM416-DB |
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48
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Special Function Blocks (continued)
Readback can be initiated at an address other than
frame 0 via the new MPI control registers (see the MPI
section for more information). In all cases, readback is
performed at sequential addresses from the start
address.
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The RD_CFG input pin is also used to control
the global 3-state (TS_ALL) function. Before and during
conguration, the TS_ALL signal is always driven by
the RD_CFG input and readback is disabled. After con-
guration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
The readback frame contains the conguration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIO outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs.
■
Do not capture data (the data written to the RAMs,
usually 0, will be read back).
■
Capture data upon entering readback.
■
Capture data based upon a congurable signal inter-
nal to the FPGA. If this signal is tied to logic 0, cap-
ture RAMs are written continuously.
■
Capture data on either options two or three above.
The readback frame has an identical format to that of
the conguration data frame, which is discussed later
in the Conguration Data Format section. If LUT mem-
ory is not used as RAM and there is no data capture,
the readback data (not just the format) will be identical
to the conguration data for the same frame. This
eases a bitwise comparison between the conguration
and readback data. The conguration header, including
the length count eld, is not part of the readback frame.
The readback frame contains bits in locations not used
in the conguration. These locations need to be
masked out when comparing the conguration and
readback frames. The development system optionally
provides a readback bit stream to compare to readback
data from the FPGA. Also note that if any of the LUTs
are used as RAM and new data is written to them,
these bits will not have the same values as the original
conguration data frame either.
Global 3-State Control (TS_ALL)
To increase the testability of the ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
conguration, the TS_ALL signal is driven by the input
pad RD_CFG. After conguration, the TS_ALL signal
can be disabled, driven from the RD_CFG input pad, or
driven by a general routing signal in the upper right cor-
ner. Before conguration, TS_ALL is active-low; after
conguration, the sense of TS_ALL can be inverted.
The following occur when TS_ALL is activated:
■
All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pull-
down disabled), and the input buffers are congured
with TTL input thresholds.
■
The TDO/RD_DATA output buffer is 3-stated.
■
The RD_CFG, RESET, and PRGM input buffers
remain active with a pull-up.
■
The DONE output buffer is 3-stated, and the input
buffer is pulled up.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-3BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E06-1BA352C | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06-1BA352I | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E06-1BM680C | 功能描述:FPGA - 现场可编程门阵列 16192 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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