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| 型号： | ORT82G5-1FN680I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 38/119页 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
25
Figure 9. Fibre Channel Link State Machine State Diagram
XAUI Link Synchronization Function
For each lane, the receive section of the XAUI link state machine incorporates a synchronization state machine that
monitors the status of the 10-bit alignment. A 10-bit alignment is done in the SERDES based on a comma charac-
ter such as K28.5. A comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that can-
not appear across the boundary between any two valid 10-bit code-groups. This property makes the comma useful
for delimiting code-groups in a serial stream.This mechanism incorporates a hysteresis to prevent false synchroni-
zation and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled
until the lane achieves synchronization. The synchronization state diagram is shown in Figure 10. This state
machine is modeled after draft IEEE 802.3ae, version 2.1 but will also operate with version 4.1 implementations.
Table 4 and Table 5 describe the state variables used in Figure 10. The XAUI state machine does not have any
control over the SERDES byte aligner. It is the user’s responsibility to control the byte aligner through software
access of register map addresses 30800 and 30900.
Note that it takes four idle ordered sets (e.g. K28.5, Dxx.y, Dxx.y, Dxx.y) to bring the state machine from a
loss_of_sync to a synch_acq’d_1 state. When back-to-back commas are used instead, it takes a total of ve com-
mas to achieve the same result as with idle ordered sets.
Table 4. XAUI Link Synchronization State Diagram – Functions
Function
Description
sync_complete
Indication that alignment code-group alignment has been established at the boundary indicated by the
most recently received comma.
cg_comma
Indication that a valid code-group, with correct running disparity, containing a comma has been received.
cg_good
Indication that a valid code-group with the correct running disparity has been received.
cg_bad
Indication that an invalid code-group has been received.
no_comma
Indication that comma timer has expired. The timer is initialized upon receipt of a comma.
LOS = 1
LAST ORDERED SET RECEIVED:
VW
RST
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1)
OS
CV
OS
CV
1VW
2 VW
a
b
c
d
e
h
g
f
LOSS OF SYNCHRONIZATION (WDSYNC_XX = 0)
LSM_ENABLE
+
POWERUP_RESET
VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION) WITH AT LEAST
CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION)
OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER)
1VW: FIRST VALID WORD AFTER A CODE VIOLATION
TWO PRECEEDING VALID WORDS
2VW: SECOND VALID WORD AFTER A CODE VIOLATION
相关PDF资料 |
PDF描述 |
|---|---|
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-1FN680I1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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