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| 型号： | ORT82G5-1FN680I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 42/119页 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
29
Figure 15. Alignment of all Eight SERDES Channels.
Note that any channel within an alignment group can be removed from that alignment group by setting
FMPU_STR_EN_xx to 0. The disabling of any channel(s) within an alignment group will not affect the operation of
the remaining active channels. If the active channels are synchronized, that synchronization will be maintained and
no data loss will occur.
For every alignment group, there are both an OVFL and an OOS status register bit. The OVFL bit is set when align-
ment FIFO overow occurs. The OOS bit is agged when the down counter in the synchronization algorithm has
reached a value of 0 and alignment characters from all channels within an alignment group have not been received.
In the memory map section for the ORT42G5 the bits indicating OOS and OVFL are referred to as
SYNC2_[A:B]_OOS and SYNC4_OOS and the bits indicating OVFL are SYNC2_[A:B]_OVFL and SYNC4_OVFL.
In the memory map section for the ORT82G5, the bits indicating OOS and OVFL are referred to as
SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS and SYNC8_OOS and the bits indicating OVFL are
SYNC2_[A1,A2,B1,B2]_OVFL, SYNC4_[A:B]_OVFL and SYNC8_OVFL.
Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices
needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading from
a second alignment FIFO until all channels requesting alignment on the current device and all channels requesting
alignment on the other device are aligned (as indicated on the K_CTRL character). These second alignment FIFOs
will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for both
devices be driven by the same signal.
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The
mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column.
Figure 16 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies
that at least ± 80 bits of skew compensation capability should be provided, which the devices signicantly exceed.
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
t0
相关PDF资料 |
PDF描述 |
|---|---|
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-1FN680I1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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