参数资料
型号: ORT82G5-1FN680I
厂商: Lattice Semiconductor Corporation
文件页数: 81/119页
文件大小: 0K
描述: IC TRANCEIVERS FPSC 680FPBGA
产品变化通告: Product Discontinuation 01/Aug/2011
标准包装: 24
系列: *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
64
30810 - Ax
30910 - Bx
[0]]
00
Reserved for future use
[1]
Reserved for future use
[2]
DOWDALIGN_xC
Word Realign Bit. When DOWDALIGN_xC transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xC.
NOWDALIGN_xC=0 on device reset.
[3]
DOWDALIGN_xC
Word Realign Bit. When DOWDALIGN_xC transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xC.
NOWDALIGN_xC=0 on device reset.
[4]
Reserved for future use. Set to zero.
[5]
Reserved for future use. Set to zero.
[6]
FMPU_STR_EN _xC
Enable multi-channel alignment for Channel xC.
When FMPU_STR_EN _xC = 0, Channel xC is not part of a multi-chan-
nel alignment group
When FMPU_STR_EN _xC = 1, Channel xC is part of a twin channel
alignment (SERDES block A or B) or quad channel alignment (both
SERDES blocks) group.
[7]
FMPU_STR_EN _xD
Enable multi-channel alignment for Channel xD.
When FMPU_STR_EN _xD = 0, Channel xD is not part of a multi-chan-
nel alignment group
When FMPU_STR_EN _xD = 1, Channel xD is part of a twin channel
alignment (SERDES block A or B) or quad channel alignment (both
SERDES blocks) group.
30811 - Ax
30911 - Bx
[0:7] FMPU_SYNMODE_
[A:B]
00
Sync mode for block [A:B]
00000000 = No channel alignment
00001010 = Twin channel alignment, SERDES block [A:B]
00001111 = Quad channel alignment (both SERDES blocks)
30820 - Ax
30920 - Bx
[0]
00
Reserved for future use.
[1]
Reserved for future use.
[2]
FMPU_RESYNC1_xC
Resync a Single Channel. When FMPU_RESYNC1_xC transitions from
0 to 1, the corresponding channel xC is resynchronized (the write and
read pointers are reset). FMPU_STR_EN_xC=0 on device reset.
[3]
FMPU_RESYNC1_xD
Resync a Single Channel. When FMPU_RESYNC1_xD transitions from
0 to 1, the corresponding channel xD is resynchronized (the write and
read pointers are reset). FMPU_STR_EN_xD=0 on device reset.
[4]
Reserved for future use.
[5]
FMPU_RESYNC2[A:B]
Resync a Twin-Channel Group. When FMPU_RESYNC2[A:B] transitions
from a 0 to a 1, the corresponding twin-channel group is resynchronized.
FMPU_RESYNC2[A:B]=0 on device reset.
[6]
Reserved for future use.
[7]
XAUI_MODE[A:B]
Controls use of XAUI link state machine in place of Fibre-Channel state
machine. When XAUI_MODE[A:B]=1, both channels in the SERDES
block enable their XAUI link state machines. (LINKSM_xx bits are
ignored). XAUI_MODE[A:B]=0 on device reset.
30821 - A
30921 - B
[0]
NOCHALGN [A:B]
00
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of
multi-channel alignment FIFOs for the corresponding SERDES quad.
NOCHALGN [A:B] =0 on device reset.
[1:7]
Reserved for future use.
Table 28. ORT42G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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