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参数资料
型号： ORT82G51BM680-DB
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装： PLASTIC, FBGA-680
文件页数： 51/109页
文件大小： 1379K
代理商： ORT82G51BM680-DB
Lattice Semiconductor
46
Data Sheet
April, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Common Transmit and Receive Channel Conguration Registers
30004
—
PRBS_AA
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel A. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AA
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
A. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AA
Transmit and Receive
Software Reset Bit,
Bank A, Channel A.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AA
Transmit and Receive Test
Enable Bit, Bank A, Channel
A. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
30014
—
PRBS_AB
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel B. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AB
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
B. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AB
Transmit and Receive
Software Reset Bit,
Bank A, Channel B.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AB
Transmit and Receive Test
Enable Bit, Bank A, Channel
B. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
30024
—
PRBS_AC
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel C. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AC
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
C. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AC
Transmit and Receive
Software Reset Bit,
Bank A, Channel C.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AC
Transmit and Receive Test
Enable Bit, Bank A, Channel
C. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
30034
—
PRBS_AD
Transmit and
Receive PRBS
Enable Bit, Bank A,
Channel D. When
PRBS = 1, the
PRBS generator on
the transmitter and
the PRBS checker
on the receiver are
enabled. PRBS = 0
on device reset.
MASK_AD
Transmit and
Receive Alarm Mask
Bit, Bank A, Channel
D. When MASK = 1,
the transmit and
receive alarms of a
channel are pre-
vented from generat-
ing an interrupt. This
MASK bit overrides
the individual alarm
mask bits in the
Alarm Mask Regis-
ters. MASK = 1 on
device reset.
SWRST_AD
Transmit and Receive
Software Reset Bit,
Bank A, Channel D.
When SWRST = 1, this
bit provides the same
function as the hard-
ware reset, except all
conguration register
settings are preserved.
This is not a self-clear-
ing bit. Once set, this bit
must be cleared by writ-
ing a 0 to it. SWRST = 0
on device reset.
————
TESTEN_AD
Transmit and Receive Test
Enable Bit, Bank A, Channel
D. When TESTEN = 1, the
transmit and receive sections
are placed in test mode.
TESTEN = 0 on device reset.
When the global test enable
bit GTESTEN = 0, the indi-
vidual channel test enable
bits are used to selectively
place a channel in test or
normal mode. When GTES-
TEN = 1, all channels are set
to test mode regardless of
their TESTEN setting.
40
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