参数资料
型号: ORT82G51BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 63/109页
文件大小: 1379K
代理商: ORT82G51BM680-DB
57
Lattice Semiconductor
Data Sheet
April, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
* TCKSEL(A,B)[0:1]
00 = Channel A
10 = Channel B
01 = Channel C
11 = Channel D
RCKSEL(A,B)[0:1]
00 = Channel A
10 = Channel B
01 = Channel C
11 = Channel D
RX_FIFO_MIN[0:4] = Bits {w, u, z, y, x}
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
Common Control Registers
30A00
C0
TCKSELA*
Controls source of 78 MHz
TCK78 for bank A
RCKSELA
Controls source of 78 MHz
RCK78 for bank A
TCKSELB
Controls source of 78 MHz
TCK78 for bank B
RCKSELB
controls source of 78 MHz
RCK78 for bank B
00
30A01
C1
Reserved for future use
RX_FIFO_MIN - Bits x, y, z
Threshold for low address in RX_FIFO’s
00
30A02
C2
RX_FIFO_MIN - Bits u, w
Threshold for low address in
RX_FIFO’s
FMPU_RESY
NC8
Resync 8
channels,
A[A:D], B[A:D]
Reserved for future use
00
Common Status Registers
30A04
C4
SYNC8_OVF
L
Alignment
FIFO over-
ow for
A[A:D], B[A:D]
SYNC8_OOS
Alignment out
of sync for
A[A:D], B[A:D]
Reserved for future use
00
30A05
C5
Reserved for future use
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