- 您现在的位置：买卖IC网 > PDF目录189449 > ORT82G51BM680-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 380000 GATES, PBGA680 PDF资料下载
参数资料
| 型号： | ORT82G51BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 55/109页 |
| 文件大小： | 1379K |
| 代理商： | ORT82G51BM680-DB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页当前第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页
Lattice Semiconductor
5
Data Sheet
April, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Programmable Features (continued)
■
Built-in testability:
— Full boundary scan (IEEE 1149.1 and Draft
1149.2 JTAG).
— Programming and readback through boundary
scan port compliant to IEEE Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode.
■
Improved built-in clock management with program-
mable phase-locked loops (PPLLs) provide optimum
clock modication and conditioning for phase, fre-
quency, and duty cycle from 20 MHz up to 420 MHz.
Multiplication of the input frequency up to 64x and
division of the input frequency down to 1/64x possi-
ble.
■
New cycle stealing capability allows a typical 15% to
40% internal speed improvement after nal place
and route. This feature also enables compliance with
many setup/hold and clock to out I/O specications
and may provide reduced ground bounce for output
buses by allowing exible delays of switching output
buffers.
Programmable Logic System Features
■
PCI local bus compliant for FPGA I/Os.
■
Improved PowerPC 860 and PowerPC II high-
speed synchronous microprocessor interface can be
used for conguration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA logic, RAMs, and embedded stan-
dard cell blocks. Glueless interface to synchronous
PowerPC processors with user-congurable address
space provided.
■
New embedded AMBA specication 2.0 AHB sys-
tem bus (ARM processor) facilitates communica-
tion among the microprocessor interface,
conguration logic, embedded block RAM, FPGA
logic, and embedded standard cell blocks.
■
Variable size bused readback of conguration data
capability with the built-in microprocessor interface
and system bus.
■
Internal, 3-state, and bidirectional buses with simple
control provided by the SLIC.
■
New clock routing structures for global and local
clocking signicantly increases speed and reduces
skew (<200 ps for OR4E4).
■
New local clock routing structures allow creation of
localized clock trees.
■
Two new edge clock routing structures allow up to six
high-speed clocks on each edge of the device for
improved setup/hold and clock to out performance.
■
New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
■
New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
■
ORCA Foundry development system software. Sup-
ported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
■
Meets universal test and operations PHY interface
for ATM (UTOPIA) levels 1, 2, and 3; as well as POS-
PHY3. Also meets proposed specications for UTO-
PIA level 4 and POS-PHY3 (2.5 Gbits/s) and POS-
PHY4 (10 Gbits/s) interface standards for packet-
over-SONET as dened by the Saturn Group.
相关PDF资料 |
PDF描述 |
|---|---|
| OSC-1B1FREQ | TCVCXO, CLIPPED SINE OUTPUT, 10 MHz - 50 MHz |
| OSC-3A110MHZ | TCVCXO, CLIPPED SINE OUTPUT, 10 MHz |
| OSC-3B219.68MHZ | TCVCXO, CLIPPED SINE OUTPUT, 19.68 MHz |
| OSC1213A | TCVCXO, SINE OUTPUT, 13 MHz |
| OSC1218D | TCVCXO, SINE OUTPUT, 12.8 MHz |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-1FN680C1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。