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| 型号： | P83C880 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 12/84页 |
| 文件大小： | 420K |
| 代理商： | P83C880 |
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1997 Dec 12
12
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
7.3
Additional Special Function Registers
The standard SFRs as used in 80C51 and the SFRs for some typical derivative functions like I
2
C-bus interface, Timer,
etc. are described in the “Data Handbook IC20” The specific SFRs for the P83C880 are introduced in the relevant
chapters. Some SFRs which are not mentioned or not dedicated to a certain function will be described in the following
sections.
All new additional SFRs used in the P83C880 are listed in Table 4. However, only some of them will be explained in detail
in Sections 7.3.1 to 7.3.7.
Table 4
Overview of additional SFRs
Notes
1.
2.
X = don’t care; even if it’s implemented.
B = both read/write and R
o
= read only; accessible for the entire byte or an individual bit. U = not implemented.
REGISTER
DESCRIPTION
ADDRESS
RESET VALUE
(1)
READ/WRITE
(2)
RAMBUF
DDCCON
DDCADR
DDCDAT
DFCON
ADCDAT
PWM10H
PWM10L
S1CON
S1STA
S1DAT
S1ADR
PWME1
PWME2
PWM0 to PWM9
RAM Buffer I/O Interface Register
DDC Control Register
DDC Address Pointer
Data Shift Register for DDC1
Miscellaneous Control Register
ADC Control Register
PWM High-byte Data Latch
PWM Low-byte Data Latch
Control Register for DDC2
Status Register for DDC2
Data Shift Register for DDC2
Address Register for DDC2
PWM Output Control Register 1
PWM Output Control Register 2
Data Latches for 8-bit PWMs
9CH
9DH
9EH
9FH
C0H
C1H
C6H
C7H
D8H
D9H
DAH
DBH
C8H
E8H
XXXXXXXX
X
00
X
0000
00000000
00000000
10000000
XX
000000
00000000
10000000
00000000
11111000
00000000
00000000
00000000
00000000
00000000
B
UBBUBBBB
B
B
B
UUBBBBBR
O
B
B
B
R
o
B
B
B
B
B
C9H to CFH,
EDH to EFH
E9H to ECH
F6H
F7H
F8H
F9H
FAH
FBH
FCH
DAC0 to DAC3
HFP
HFPOPW
MDCST
VFP
VFPOPW
PULCNT
HFHIGH
8-bit Data Latches for 8-bit DACs
Free run Control Register for HSYNC
out
Free run and Pulse width for HSYNC
out
Mode Detect Control and Status Register
Free run Control Register for VSYNC
out
Free run and Pulse width for VSYNC
out
Pulse Generation Control Register
Horizontal Period Counting High-byte
Register
Vertical Period Counting High-byte Register
Vertical and Horizontal Period Counting
Low-nibbles Register
Watchdog Timer Data Register
00000000
01100000
00011111
1
X
000000
01000000
XX
000101
00000000
00000000
B
B
B
BUBBRRRR
B
B
B
R
o
VFHIGH
VFLHFL
FDH
FEH
00000000
00000000
R
o
R
o
T2
FFH
00000000
B
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