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| 型号： | P83C880 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 24/84页 |
| 文件大小： | 420K |
| 代理商： | P83C880 |
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1997 Dec 12
24
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
11 REDUCED POWER MODES
Two software selectable modes of reduced power
consumption are implemented. These are the Idle mode
and the Power-down mode.
11.1
Power Control Register (PCON)
The Idle mode and Power-down mode are activated by
software via the Power Control Register (SFR PCON).
Its hardware address is 87H. PCON is not bit addressable.
The reset value of PCON is 00H.
11.2
Idle mode
Idle mode operation permits the interrupts, I
2
C-bus
interface, DDC interface, mode detection and timer blocks
T0, T1 and T2 (Watchdog Timer) to function while the CPU
is halted. The following functions are switched off when the
microcontroller enters the Idle mode:
CPU (halted)
PWM0 to PWM10 (reset, output = HIGH)
4-bit ADC (aborted if conversion is in progress)
DAC0 to DAC3 (output = indeterminate or frozen at the
final value prior to the Idle instruction; decided by
software).
The following functions remain active during Idle mode;
these functions may generate an interrupt or reset and
thus terminate the Idle mode:
Timer 0, Timer 1 and Timer 2 (Watchdog Timer)
The DDC interface
External interrupt
Mode detection.
The instruction that sets PCON.0 is the last instruction
executed in the normal operating mode before Idle mode
is activated. Once in the Idle mode, the CPU status is
preserved in its entirety: the Stack Pointer, Program
Counter, Program Status Word, Accumulator, RAM and all
other registers maintain their data during Idle mode.
The status of external pins during Idle mode is shown in
Table 28.
There are three ways to terminate the Idle mode:
Activation of any enabled interrupt X0, T0, X1, T1 or S1
will cause PCON.0 to be cleared by hardware
terminating Idle mode. The interrupt is serviced, and
following return from interrupt instruction RETI, the next
instruction to be executed will be the one which follows
the instruction that wrote a logic 1 to PCON.0.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear
both flag bits. When Idle mode is terminated by an
interrupt, the service routine can examine the status of
the flag bits.
The second way of terminating the idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation.
The third way of terminating the Idle mode is by an
internal watchdog reset.
In all cases the microcontroller restarts after 3 machine
cycles.
11.3
Power-down mode
In Power-down mode the system clock is halted. The
oscillator is frozen after setting the bit PD in the PCON
register.
The instruction that sets PCON.1 is the last executed prior
to going into the Power-down mode. Once in Power-down
mode, the oscillator is stopped.The content of the on-chip
RAM and the Special Function Registers are preserved.
Note that Power-down mode can not be entered when the
Watchdog Timer has been enabled.
The Power-down mode can be terminated by an external
reset in the same way as in the 80C51 (but the SFRs are
cleared due to RESET) or in addition by the external
interrupt, INT1.
A termination with INT1 does not affect the internal data
memory and the Special Function Registers. This gives
the possibility to exit from Power-down without changing
the port output levels. To terminate the Power-down mode
with an external interrupt, INT1 must be switched to be
level-sensitive and must be enabled. The external interrupt
input signal INT1 must be kept LOW till the oscillator has
restarted and stabilized. The instruction following the one
that put the device into the Power-down mode will be the
first one which will be executed after the wake-up.
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