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| 型号： | P83C880 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 51/84页 |
| 文件大小： | 420K |
| 代理商： | P83C880 |
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1997 Dec 12
51
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
19 HARDWARE MODE DETECTION
Due to the many restrictions for mode detection via
software, a hardware mode detector is introduced in the
P83C880. This feature has the following advantages:
Fast enough to react on any mode change.
Possibility to detect the polarity of HSYNC without extra
input pin.
Higher accuracy to measure the HSYNC and VSYNC
frequency
Relieves the CPU and valuable timers/counters in the
microcontroller from lengthy mode detection
In reduced power modes, e.g. Idle mode, the mode
detection is still active.
Apart from the above mentioned benefits, some extra
features can be achieved through hardware mode
detection. The composite sync separation can be done
while mode detection continues. The various formats of
HSYNC and VSYNC output pulses are provided to fit into
different applications.
Since the information of the operational modes defined in
Device Power Management Signalling (DPMS) for
monitors is embedded in HSYNC and VSYNC, the mode
detector is also able to recognize the operational mode
and generate the fixed free running frequency for HSYNC
and VSYNC in some specific modes like stand-by,
suspend and power-off. Two display patterns, the white
and the cross hatch, can be displayed for the self test in
the free running mode.
More on Device Power Management Signalling (DPMS)
will be explained in Chapter 20, “Power management”.
19.1
Special Function Register for mode detection
and sync separation
There are 4 SFRs related to mode detection and sync
separation: MDCST (SFR address F8H); HFHIGH (SFR
address FCH); VFHIGH (SFR address FDH) and VFLHFL
(SFR address FEH).
Five SFRs are applied for the output pulse generation of
HSYNC and VSYNC and the display pattern generation for
the self test: HFP (SFR address F6H); HFPOPW (SFR
address F7H); VFP (SFR address F9H); VFPOPW (SFR
address FAH) and PULCNT (SFR address FBH).
These SFRs are described in detail in Section
19.1.1 to 19.1.9.
19.1.1
M
ODE
D
ETECTION
/
SYNC SEPARATION
C
ONTROL AND
S
TATUS
R
EGISTER
(MDCST)
Table 43
Mode Detection/sync separation Control and Status Register (SFR address F8H)
Table 44
Description of MDCST bits
7
6
5
4
3
2
1
0
MARCH
CHREQ
XSEL
HSEL
Hpres
Vpres
Hpol
Vpol
BIT
SYMBOL
DESCRIPTION
7
MARCH
Mode detection enable
. If MARCH = 1, mode detection is enabled. If MARCH = 0,
mode detection is disabled. Default value MARCH = 1 to guarantee that mode detection
is automatically executed after power-on reset.
Polarity or frequency change. If CHREQ = 1 then the polarity or frequency change
happened. The polarity or frequency is detected after a CHREQ HIGH-to-LOW transition,
because the mode change becomes stable after the CHREQ HIGH-to-LOW transition.
Indicates if the clock used for the mode detection and the pulse generation is
1
2
×
f
clk
.
If XSEL = 1, the internal clock is
1
2
×
f
clk
. If XSEL = 0 the internal clock is equal to f
clk
.
Indicates the horizontal sync input coming from HSYNC
in
(pin HSYNC
in
/PROG) or
CSYNC
in
(pin CSYNC
in
/P1.6). If HSEL = 1, CSYNC
in
is the input pin. If HSEL = 0,
HSYNC
in
is the input pin.
Indicates the presence of HSYNC. If Hpres = 1, HSYNC is present. If Hpres = 0, HSYNC
is not present.
6
CHREQ
5
XSEL
4
HSEL
3
Hpres
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