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| 型号： | P83C880 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 59/84页 |
| 文件大小： | 420K |
| 代理商： | P83C880 |
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1997 Dec 12
59
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
A 12-bit counter is used to measure the frequency of
HSYNC. Every 4 HSYNC periods are measured and
compared with the previous locked HSYNC frequency; the
counter is reset every 4 HSYNC periods. The base clock
--------1
to the counter is
for a 12 MHz system
clock. If the new HSYNC frequency is larger than the
previous HSYNC frequency, there is a 4-bit counter to
avoid the noise or the temporary frequency shift.
When the 4-bit counter counts up to 15 for the comparison
Hfreq
(new)
> Hfreq
(previous)
, then the mode change interrupt
is issued. The time from mode change to interrupt issued
is approximately 4
×
Hperiod
(new)
×
15 or
(4
×
Hperiod
(new)
×
14) + n
×
Hperiod
(previous)
),
where n = 1, 2 or 3.
If the new HSYNC frequency is not in the static state and
is smaller than the previous HSYNC frequency, the time
from mode change to interrupt issued is approximately
(4
×
Hperiod
(new)
×
3)
(n
×
Hperiod
(previous)
), where
n = 1, 2, 3 or 4. The static state is considered as the state
where the 12-bit counter, for measuring the HSYNC
frequency, reaches 4080.
For a 12 MHz system clock, the static state is equal to
4
.
If the input HSYNC frequency is less than 11.8 kHz, it will
be regarded as static state. A 2-bit counter is used to avoid
the noise or the temporary shift.
When the 2-bit counter counts up to 3 for the comparison
‘static state’ < Hfreq
(new)
< Hfreq
(previous)
, then the mode
change interrupt is issued.
83 ns
=
83ns
4080
×
---------------1
84660 ns
---------1
11.8 kHz
=
=
When the new input HSYNC is changed to a static state,
the HSYNC frequency counter reaches 4080. In order to
have a faster response of the mode change interrupt, the
2-bit counter is not used and the mode change interrupt is
issued immediately. The time from mode change to
interrupt issued is approximately
((4080 + 5)
×
83 ns)
(n
×
Hperiod
(previous)
), where
n = 1, 2, 3 or 4.
19.2.5.2
Parameter Hpres
The presence indicator Hpres, as stored in the SR flip-flop,
contains some hysteresis, as required due to the two
threshold settings in the comparator. The SR flip-flop will
be set, indicating that no active sync (or sync with a too low
frequency) is coming in if the counter reaches a value of
FF0H (4080 decimal). The corresponding horizontal sync
frequency is:
FOSH
×
The SR flip-flop will be reset, indicating that an active sync
is present, if the counter reaches a value lower than FC0H
(4032 decimal). The corresponding horizontal sync
frequency is:
FOSH
×
Counter value
(
The hysteresis result,
Hysteresis
,
is shown in Table 64.
f
H
Hfreq1
)
--Counter value
4
FOSH
4080
×
=
=
=
f
H
Hfreq2
)
---------4
4
FOSH
4032
×
=
=
=
Hfreq1
Hfreq2
–
(
)
Hfreq1
=
Table 64
Hysteresis in the Hpres detection
XTAL (f
clk
)
(MHz)
FOSH
(MHz)
Hfreq1
(MHz)
Hfreq2
(MHz)
HYSTERESIS
(%)
10
12
16
10
12
8
9.804
11.765
7.843
9.921
11.905
7.937
1.2
1.2
1.2
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