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| 型号： | P83C880 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 63/84页 |
| 文件大小： | 420K |
| 代理商： | P83C880 |
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1997 Dec 12
63
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
19.2.11 T
HE
D
ISPLAY
P
ATTERN
G
ENERATION
For certain events such as disconnection with the host or
the life test of monitor sets, it is convenient to have certain
display patterns shown on the monitor as the indication of
the operation of the monitor. The P83C880 provides two
simple patterns, the white pattern and the cross hatch
pattern for this purpose in the free running mode.
In the free running mode, the intervals of HSYNC and
VSYNC are determined by the 10-bit registers, HFP and
VFP. Based on the HFP and VFP, the internal down
counter will determine the starting or ending of the HSYNC
and VSYNC. The starting position, ending position and the
duration of the adjacent hatch lines are all related to the
programmed value of HFP and VFP. As a matter of fact,
the starting and ending position of the white pattern are
decided by the fixed number of FOSH clock and FOSV
clock (see Fig.31). Therefore, the position or dimension of
the white pattern is much related to HFP and VFP. The
duration of every two hatch lines (accordingly, the number
of hatch lines in the horizontal or vertical direction) will
depend on two fixed numbers (32, 32) which divide HFP
and VFP. For both white and cross hatch patterns, the
displayed pattern might look different in the different timing
modes and the symmetric display is not guaranteed.
However, they should be sufficient to be used as the
indicator to report the status of the monitor. Figure 31
demonstrates the display of the two patterns.
Two flags: PATENA (SFR PWME2) and PATTYP (SFR
PULCNT), are used to control the pattern display; for
detailed usage of those control bits refer to Section 7.3.6
and Section 19.1.9.
Fig.31 Two self test display patterns.
handbook, full pagewidth
MGG040
32
HPST
32
HPST
16
HPST
32 FOSH
16 FOSH
32 FOSH
32 FOSH
2. THE CROSS HATCH
1. THE WHITE PATTERN
16 FOSH
19.2.12 CLAMP
OUTPUT
To facilitate the video processing in the following stage, the
clamping pulse can be delivered on pin
PWM8/CLAMP/P3.0 by setting flag CLMPEN (PULCNT.7)
to HIGH. The clamping pulse always accompanies the
HSYNC
out
pulse. Therefore, even in the free running mode
the clamping pulse is still present as long as the CLMPEN
bit is set. Flag FBPO (PULCNT.1) can be used to choose
the front porch clamp pulse (FBPO = 0) or the back porch
clamp pulse (FBPO = 1). The pulse width of the clamping
output signal is fixed to 8 FOSH clocks.
The bit PHSI (PULCNT.0) is used to set the output polarity
of HSYNC
out
and the clamping pulse. If PHSI is LOW then
the output polarity will be positive, otherwise the output
polarity is negative.
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