参数资料
| 型号： | PCF8562TT/S400/2,1 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 16/43页 |
| 文件大小： | 0K |
| 描述： | IC LCD DRIVER 48-TSSOP |
| 标准包装： | 2,000 |
| 显示器类型： | LCD |
| 配置： | 7段 + DP，14段 + DP + AP，点阵 |
| 接口： | I²C，2 线串口 |
| 数字或字符： | 8 个字符，16 个字符 |
| 电流 - 电源： | 8µA |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | PCF8562TTS40021 |
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NXP Semiconductors
PCF8562
the internal or an external clock: f fr = ------- .
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal
oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC
to pin V SS .
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to V DD .
The LCD frame signal frequency is determined by the clock frequency (f clk ).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8562 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
f clk
24
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
? In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these
two adjacent outputs can be tied together to give enhanced drive capabilities.
? In the 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the
same signals and may also be paired to increase the drive capabilities.
? In the static drive mode the same signal is carried by all four backplane outputs and
they can be connected in parallel for very high drive requirements.
PCF8562
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 June 2011
? NXP B.V. 2011. All rights reserved.
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| PCF8563 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Real-time clock/calendar |
| PCF8563_11 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Real-time clock/calendar |
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| PCF8563BS/4,118 | 功能描述:实时时钟 ULTRA LOW POWER RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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